Information

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller PBGA 516 (27x27) 32-Bit 264 MHz I/O number 32

Introduction

This report applies to mask 3M17W for these products:

• MPC5674F

Errata ID Errata Title

3521 DECFIL: Soft reset failures at the end of filtering

6026 DSPI: Incorrect SPI Frame Generated in Combined Serial Interface Configuration

818 EMIOS/ETPU: Global timebases not synchronized

3378 EQADC: Pull devices on differential pins may be enabled for a short period of time during and just after

POR

5642 ETPU2: Limitations of forced instructions executed via the debug interface

6309 ETPU2: STAC bus timebase export to peripherals does not work if the ratio of eTPU clock to peripheral

clock is 2:1.

2740 ETPU2: Watchdog Status Register (WDSR) may fail to update on channel timeout

5640 ETPU2: Watchdog timeout may fail in busy length mode

2382 FLASH: Flash Array Integrity Check

1312 FLASH: MCR[DONE] bit may be set before high voltage operation completes when executing a suspend

sequence

3659 FLASH: Resuming after a suspend during an Erase may prevent the erase from completing.

3407 FlexCAN: CAN Transmitter Stall in case of no Remote Frame in response to Tx packet with RTR=1

2424 FlexCAN: switching CAN protocol interface (CPI) to system clock has very small chance of causing the

CPI to enter an indeterminate state

1364 FlexRay : Message Buffer Slot Status corrupted after system memory access timeout or illegal address

access

1369 FlexRay : Message Buffer Status, Slot Status, and Data not updated after system memory access timeout

or illegal address access

2302 FlexRay: Message Buffer can not be disabled and not locked after CHI command FREEZE

6726 NPC: MCKO clock may be gated one clock period early when MCKO frequency is programmed as

SYS_CLK/8.and gating is enabled

Table continues on the next page...

Freescale Semiconductor

MPC5674F_3M17W

Mask Set Errata

Rev 13 SEP 2013

Mask Set Errata for Mask 3M17W

Summary of content (17 pages)

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Freescale Semiconductor Mask Set Errata MPC5674F_3M17W Rev 13 SEP 2013 Mask Set Errata for Mask 3M17W Introduction This report applies to mask 3M17W for these products: • MPC5674F Errata ID Errata Title 3521 DECFIL: Soft reset failures at the end of filtering 6026 DSPI: Incorrect SPI Frame Generated in Combined Serial Interface Configuration 818 EMIOS/ETPU: Global timebases not synchronized 3378 EQADC: Pull devices on differential pins may be enabled for a short period of time during and just af
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Errata ID Errata Title 3553 NXFR: Flexray databus translates into unexpected data format on the Nexus interface 1279 NZ7C3:Core Nexus Read/Write Access registers cleared by system reset 7120 NZxC3: DQTAG implemented as variable length field in DQM message 2696 PBRIDGE: Write buffer may cause overflow/underflow of DMA transfers 2996 PIT_RTI: RTI timer corruption when debugging 2322 PMC: LVREH/LVREA/LVRE50 may exit LVI triggered reset with LVI condition still existing 3377 Pad Ring:Nexus pins m
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Description: In the Combined Serial Interface (CSI) configuration of the Deserial Serial Peripheral Interface (DSPI) where data frames are periodically being sent (Deserial Serial Interface, DSI), a Serial Peripheral Interface (SPI) frame may be transmitted with incorrect framing. The incorrect frame may occur in this configuration if the user application writes SPI data to the DSPI Push TX FIFO Register (DSPI_PUSHR) during the last two peripheral clock cycles of the Delay-after-Transfer (DT) phase.
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1- Clear the Global Time Base Enable (GTBE) bit in the eTPU Module Configuration Register (ETPUMCR[GTBE] = 0). 2- Clear the Global Time Base Enable (GTBE) and Global Prescaler Enable (GPREN) bits in the eMIOS Module Configuration Register (EMIOS_MCR[GTBE] = 0, EMIOS_MCR[GPREN] = 0) to stop the Global Clock Prescaler (GCP) from counting. 3- Write the desired counter values to the eTPU Time Counter Registers 1 and 2 (TCR1 and TCR2) with eTPU microcode (these registers cannot be written by the CPU).
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Increment the PC value stored in the RAR by executing a forced Arithmetic Logic Unit (ALU) instruction after the execution of the branch or dispatch call instruction. Workaround for limitation #2 (CIRC): To force an interrupt or DMA request from the debugger: 1- Program a Shared Code Memory (SCM) location with an instruction that issues the interrupt and/or DMA request. Note: Save the original value at the SCM location. 2- Save the address of the next instruction to be executed.
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e5640: ETPU2: Watchdog timeout may fail in busy length mode Errata type: Errata Description: When the Enhanced Time Processing Unit (eTPU) watchdog is programmed for busy length mode (eTPU Watchdog Timer Register (ETPU_WDTR) Watchdog Mode field (WDM) = 3), a watchdog timeout will not be detected if all of the conditions below are met: 1- The watchdog timeout occurs at the time slot transition, at the first instruction of a thread, or at the thread gap.
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Workaround: Because the MCR[DONE] flag can be set too soon, a delay needs to be inserted between setting the MCR[ESUS] or MCR[PSUS] and reading the same flash partition. The minimum duration of the delay should be 40us to guarantee correct operation. The Freescale flash programming driver includes this workaround. e3659: FLASH: Resuming after a suspend during an Erase may prevent the erase from completing.
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c) Any MB (despite of being Tx or Rx) is reconfigured (by writing its CS field) just after the Intermission field. d) A new incoming message sent by any external node starts just after the Intermission field. Workaround: Do not configure the last MB as a Remote Answer (with code "a").
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Description: If a message buffer is assigned to the last slot in a FlexyRay communication cycle and a system memory access timeout or illegal address access occurs during the system memory access in this slot, it is possible that for all future communication 1) no slot status information will be written, 2) the message buffer status will not be updated, and 3) no message frames will be received. If this happens, several message buffers can never be locked by the application.
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Workaround: Expect to receive the MCKO edge corresponding to the IDLE state upon re-enabling of MCKO after MCKO has been gated. e3553: NXFR: Flexray databus translates into unexpected data format on the Nexus interface Errata type: Errata Description: The data format for Nexus Flexray messages is in little-endian (least significant byte first) order. This is not currently documented and may be unexpected for users of Power Architecture devices.
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If buffered writes are enabled in the PBRIDGE, there are certain conditions where the DMA's acknowledge is asserted before the actual write operation to the peripheral has occurred. The net effect is the DMA request is not negated properly, causing the DMA to reactivate the channel, overwriting the last transferred data value before it is transferred to the peripheral.
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e1419: SIU: Reverting ENGCLK source to the system clock has a very small chance of causing the ENGCLK generator to enter an indeterminate state Errata type: Errata Description: The reset value for the Engineering Clock (ENGCLK) source is the system clock.
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Workaround: Do not place code to be executed within the last 64 bytes of a memory region. When executing code from internal ECC SRAM, initialize memory beyond the end of the code until the next 32byte aligned address and then an additional 64 bytes to ensure that prefetches cannot land in uninitialized SRAM.
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Note 3: When using an odd prescaler (ADCx_CLK_ODD = 1), the duty cycle setting (ADCxCLK_DTY) must be kept at the default setting of 0.
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e2396: eSCI : Stop Mode not entered in LIN mode Errata type: Errata Description: When the eSCI module is in LIN mode and transmits the Header of an LIN RX frame, if the CPU requests Stop Mode, the eSCI module may not acknowledge the Stop Mode request and will stay in Normal Operating Mode (not in lower power stop mode).
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Description: If the eSCI module is in LIN mode and is transmitting a LIN frame, and the application sets and subsequently clears the LIN reset bit (LRES) in the LIN Control register 1 (ESCI_LCR1), the next LIN frame transmission might incorrectly signal the occurrence of bit errors (ESCI_IFSR1[BERR]) and frame error (ESCI_IFSR1[FE]), and the transmitted frame might be incorrect. Workaround: There is no generic work around.
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