Information

Workaround: Expect to receive the MCKO edge corresponding to the IDLE state upon re-enabling of MCKO
after MCKO has been gated.
e3553: NXFR: Flexray databus translates into unexpected data format on the Nexus
interface
Errata type: Errata
Description: The data format for Nexus Flexray messages is in little-endian (least significant byte first)
order. This is not currently documented and may be unexpected for users of Power
Architecture devices.
For example, in the case of a Flexray System Memory write within the address space
determined by Data Trace Start and Data Trace End Addresses (DTSAx/DTEAx) with the data:
0x1122, the Flexray Nexus interface generates Data Trace Messages (DTM) containing the
data: 0x2211.
Workaround: The user must be aware of the data format. This will be documented in a future release of the
device reference manual.
e1279: NZ7C3:Core Nexus Read/Write Access registers cleared by system reset
Errata type: Errata
Description: The e200z7 Nexus Read/Write Access registers are cleared when system reset is asserted.
This affects the Read/Write Access Data register (RWD), the Read/Write Access Address
register (RWA), and the Read/write Access Control/Status register (RWCS).
Workaround: Do not expect RWD, RWCS, and RWA to retain values after reset. After reset reload any
values required for a transfer.
e7120: NZxC3: DQTAG implemented as variable length field in DQM message
Errata type: Errata
Description: The e200zx core implements the Data Tag (DQTAG) field of the Nexus Data Acquisition
Message (DQM) as a variable length packet instead of an 8-bit fixed length packet. This may
result in an extra clock ("beat") in the DQM trace message depending on the Nexus port width
selected for the device.
Workaround: Tools should decode the DQTAG field as a variable length packet instead of a fixed length
packet.
e2696: PBRIDGE: Write buffer may cause overflow/underflow of DMA transfers
Errata type: Errata
Description: Peripheral-paced DMA transfers are controlled by a hardware handshake protocol: when the
peripheral requires a data transfer, it asserts a request to the DMA. The DMA recognizes the
request, activates the corresponding channel and performs the data transfer, reading from the
source and writing to the destination. As the write is being processed, the DMA sends an
acknowledge back to the peripheral so it can negate its request.
Mask Set Errata for Mask 3M17W, Rev 13 SEP 2013
10 Freescale Semiconductor, Inc.