Information

If buffered writes are enabled in the PBRIDGE, there are certain conditions where the DMA's
acknowledge is asserted before the actual write operation to the peripheral has occurred. The
net effect is the DMA request is not negated properly, causing the DMA to reactivate the
channel, overwriting the last transferred data value before it is transferred to the peripheral.
Workaround: Do not enable buffered writes for the eDMA in the Peripheral Bridge Master Privilege Control
registers (PBRIDGE_A_MPCR and PBRIDGE_B_MPCR), by leaving the MBW4 (eDMA A
master) and MBW5 (eDMA B master) bits cleared. This is the default state of these bits, which
disables buffered writes to the peripherals from both eDMA masters.
e2996: PIT_RTI: RTI timer corruption when debugging
Errata type: Errata
Description: In rare cases, due to a synchronization issue, the Real-Time Interrupt (RTI) timer value may
become corrupted when a breakpoint occurs and the freeze bit is set to pause the timers in
debug mode (PIT_RTI_MCR[FRZ]=0b1).
None of the other timers in the PIT_RTI module are affected. During normal operation (without
debugger attached) there is no impact to the application.
Workaround: When debugging code utilizing the RTI, do not depend on the value of the RTI timer being
correct.
e2322: PMC: LVREH/LVREA/LVRE50 may exit LVI triggered reset with LVI condition
still existing
Errata type: Information
Description: After asserting the Low Voltage Reset Enables PMC_CFGR[LVREH], PMC_CFGR[LVREA],
PMC_CFGR[LVRE50] bits in the PMC, if the voltage ramps down below the LVI voltage on
VDDEHx, VDDA or VDDREG respectively, the part will go to a short power on reset (POR).
After the reset counter has expired, the device will go into normal operation, even though one
or more of the affected supplies may still be below the specified LVI voltage.
Workaround: The part will recover into normal operation, however software should check the status of the
LVIs for those segments that are required for further operation.
e3377: Pad Ring:Nexus pins may drive an unknown value immediately after power up
but before the 1st clock edge
Errata type: Errata
Description: The Nexus Output pins (Message Data outputs 0:15 [MDO] and Message Start/End outputs
0:1 [MSEO]) may drive an unknown value (high or low) immediately after power up but before
the 1st clock edge propagates through the device (instead of being weakly pulled low). This
may cause high currents if the pins are tied directly to a supply/ground or any low resistance
driver (when used as a general purpose input [GPI] in the application).
Workaround: 1. Do not tie the Nexus output pins directly to ground or a power supply.
2. If these pins are used as GPI, limit the current to the ability of the regulator supply to
guarantee correct start up of the power supply. Each pin may draw upwards of 150mA.
If not used, the pins may be left unconnected.
Mask Set Errata for Mask 3M17W, Rev 13 SEP 2013
Freescale Semiconductor, Inc. 11