Information

Workaround: Do not place code to be executed within the last 64 bytes of a memory region. When executing
code from internal ECC SRAM, initialize memory beyond the end of the code until the next 32-
byte aligned address and then an additional 64 bytes to ensure that prefetches cannot land in
uninitialized SRAM.
To guard against the possibility of the BAM causing a machine-check exception to be taken, as
noted in the errata description, user application code should check and clear the Machine
Check Syndrome Register (MCSR) in the core before enabling the machine check interrupt.
This can be done by writing all 1s to MCSR.
e6966: eDMA: Possible misbehavior of a preempted channel when using continuous
link mode
Errata type: Errata
Description: When using Direct Memory Access (DMA) continuous link mode Control Register Continuous
Link Mode (DMA_CR[CLM]) = 1) with a high priority channel linking to itself, if the high priority
channel preempts a lower priority channel on the cycle before its last read/write sequence, the
counters for the preempted channel (the lower priority channel) are corrupted. When the
preempted channel is restored, it continues to transfer data past its "done" point (that is the
byte transfer counter wraps past zero and it transfers more data than indicated by the byte
transfer count (NBYTES)) instead of performing a single read/write sequence and retiring.
The preempting channel (the higher priority channel) will execute as expected.
Workaround: Disable continuous link mode (DMA_CR[CLM]=0) if a high priority channel is using minor loop
channel linking to itself and preemption is enabled. The second activation of the preempting
channel will experience the normal startup latency (one read/write sequence + startup) instead
of the shortened latency (startup only) provided by continuous link mode.
e4480: eQADC: Differential conversions with 4x gain may halt command processing
Errata type: Errata
Description: If the four times amplifier is enabled for a differential analog-to-digital conversion in the
Enhanced Queued Analog to Digital Converter (eQADC) and the ADC clock prescaler is set to
divide by 12 or greater, then the ADC will stop processing commands if a conversion
command is executed immediately after a differential, gain 4x conversion.
Workaround: 1) Do not use a prescaler divide factor greater than or equal to 12 (11 can be used on devices
that support odd prescalers).
2) Insert a dummy write command to any internal ADC register after every 4x conversion
command.
Note 1: If the command FIFO preemption feature is used and it is possible to preempt a FIFO
which contains the 4x conversion + dummy write workaround, then the preempting command
FIFO must be loaded FIRST with a dummy write command and then the desired preempting
conversion command in order to avoid the possibility of following a 4x conversion command
with another conversion command in the same ADC.
Note 2: The level sensitive triggers (when in Low/High Level Gated External Trigger, Single/
Continuous Scan modes) can interrupt the command sequence at any point in time, potentially
breaking the safe sequence 4x conversion command -> dummy write command.
Mask Set Errata for Mask 3M17W, Rev 13 SEP 2013
Freescale Semiconductor, Inc. 13