Information

Description: In the Combined Serial Interface (CSI) configuration of the Deserial Serial Peripheral Interface
(DSPI) where data frames are periodically being sent (Deserial Serial Interface, DSI), a Serial
Peripheral Interface (SPI) frame may be transmitted with incorrect framing.
The incorrect frame may occur in this configuration if the user application writes SPI data to the
DSPI Push TX FIFO Register (DSPI_PUSHR) during the last two peripheral clock cycles of the
Delay-after-Transfer (DT) phase. In this case, the SPI frame is corrupted.
Workaround: Workaround 1: Perform SPI FIFO writes after halting the DSPI.
To prevent writing to the FIFO during the last two clock cycles of DT, perform the following
steps every time a SPI frame is required to be transmitted:
Step 1: Halt the DSPI by setting the HALT control bit in the Module Configuration Register
(DSPI_MCR[HALT]).
Step 2: Poll the Status Register's Transmit and Receive Status bit (DSPI_SR[TXRXS]) to
ensure the DSPI has entered the HALT state and completed any in-progress transmission.
Alternatively, if continuous polling is undesirable in the application, wait for a fixed time interval
such as 35 baud clocks to ensure completion of any in-progress transmission and then check
once for DSPI_SR[TXRXS].
Step 3: Perform the write to DSPI_PUSHR for the SPI frame.
Step 4: Clear bit DSPI_MCR[HALT] to bring the DSPI out of the HALT state and return to
normal operation.
Workaround 2: Do not use the CSI configuration. Use the DSPI in either DSI-only mode or
SPI-only mode.
Workaround 3: Use the DSPI's Transfer Complete Flag (TCF) interrupt to reduce worst-case
wait time of Workaround 1.
Step 1: When a SPI frame is required to be sent, halt the DSPI as in Step 1 of Workaround 1
above.
Step 2: Enable the TCF interrupt by setting the DSPI DMA/Interrupt Request Select and
Enable Register's Transmission Complete Request Enable bit (DSPI_RSER[TCF_RE])
Step 3: In the TCF interrupt service routine, clear the interrupt status (DSPI_SR[TCF]) and the
interrupt request enable (DSPI_RSER[TCF_RE]). Confirm that DSPI is halted by checking
DSPI_SR[TXRXS] and then write data to DSPI_PUSHR for the SPI frame. Finally, clear bit
DSPI_MCR[HALT] to bring the DSPI out of the HALT state and return to normal operation.
e818: EMIOS/ETPU: Global timebases not synchronized
Errata type: Errata
Description: The eTPU and eMIOS timebases can be started synchronously by asserting the Global Time
Base Enable (GTBE) bit in either the eTPU Module Configuration Register (eTPUMCR) or the
eMIOS Module Configuration Register (eMIOS_MCR). GTBE bits from the eMIOS and eTPU
are ORed together such that asserting either of them allows both eMIOS and eTPU timebases
to start running simultaneously.
When the timebases are running and GTBE is cleared, the timebase and eTPU Angle Counter
(EAC) prescalers can stop at any count. When GTBE is reasserted, the prescalers must have
a determined initialization value so that the timebases will remain in sync with each other.
Workaround: Perform the following steps in sequence to synchronize the time base between the eTPU and
the eMIOS:
Mask Set Errata for Mask 3M17W, Rev 13 SEP 2013
Freescale Semiconductor, Inc. 3