Information

1- Clear the Global Time Base Enable (GTBE) bit in the eTPU Module Configuration Register

(ETPUMCR[GTBE] = 0).

2- Clear the Global Time Base Enable (GTBE) and Global Prescaler Enable (GPREN) bits in

the eMIOS Module Configuration Register (EMIOS_MCR[GTBE] = 0, EMIOS_MCR[GPREN] =

0) to stop the Global Clock Prescaler (GCP) from counting.

3- Write the desired counter values to the eTPU Time Counter Registers 1 and 2 (TCR1 and

TCR2) with eTPU microcode (these registers cannot be written by the CPU). This step is

required even if the values in TCR1 and TCR2 are not changed.

4- Clear the Unified Channel Prescaler Enable (UCPREN) bit in the eMIOS Channel Control

5- If it is necessary to set the eMIOS counters to known values, configure each eMIOS channel

for General Purpose Input (GPI) mode (EMIOS_CCRn[MODE] = 0000000), write the desired

counter values, and restore the desired operational mode (EMIOS_CCRn[MODE] = xxxxxxx).

6- Set the UCPREN bit in the EMIOS_CCRn register for each of the eMIOS channels

(EMIOS_CCRn[UCPREN] = 1) to re-enable the unified channel prescaler.

7- Set the GTBE and GPREN bits in the eMIOS MCR simultaneously with a single write

operation(EMIOS_MCR = EMIOS_MCR | 0x14000000).

Note: This works only for eTPU and single eMIOS module synchronization. For more than one

eMIOS module there is no workaround, since their GPREN bits cannot be written at the same

time.

e3378: EQADC: Pull devices on differential pins may be enabled for a short period of

time during and just after POR

Errata type: Errata

Description: The programmable pull devices (up and down) on the analog differential inputs of the eQADC

may randomly be enabled during the internal Power On Reset (POR) and until the 1st clock

edge propagates through the device. After the first clock edge, the pull resistors will be

disabled until software enables them.

Workaround: Protect any external devices connected to the differential analog inputs. The worst case

condition is with a 1.4K ohm resistor to VDDA (5K pull-up enabled) or VSSA (5K pull-down

enabled). This may also cause temporary additional current requirements on the VDDA supply

of each eQADC module, up to 15 mA on each eQADC if both the pull up and pull down

resistors are enabled simultaneously on all of the differential analog pins.

e5642: ETPU2: Limitations of forced instructions executed via the debug interface

Errata type: Information

Description: The following limitations apply to forced instructions executed through the Nexus debug

interface on the Enhanced Time Processing Unit (ETPU):

1- When a branch or dispatch call instruction with the pipeline flush enabled (field FLS=0) is

forced (through the debug port), the Return Address Register (RAR) is updated with the

current program counter (PC) value, instead of PC value + 1.

2- The Channel Interrupt and Data Transfer Requests (CIRC) instruction field is not

operational.

Workaround: Workaround for limitation #1 (branch or dispatch call instruction):

Mask Set Errata for Mask 3M17W, Rev 13 SEP 2013

4 Freescale Semiconductor, Inc.