Information

Increment the PC value stored in the RAR by executing a forced Arithmetic Logic Unit (ALU)
instruction after the execution of the branch or dispatch call instruction.
Workaround for limitation #2 (CIRC):
To force an interrupt or DMA request from the debugger:
1- Program a Shared Code Memory (SCM) location with an instruction that issues the interrupt
and/or DMA request. Note: Save the original value at the SCM location.
2- Save the address of the next instruction to be executed.
3- Force a jump with flush to the instruction position.
4- Single-step the execution.
5- Restore the saved value to the SCM location (saved in step 1).
6- Force a jump with flush to the address of the next instruction to be executed (saved in step
2).
NOTE: This workaround cannot be executed when the eTPU is in HALT_IDLE state.
e6309: ETPU2: STAC bus timebase export to peripherals does not work if the ratio of
eTPU clock to peripheral clock is 2:1.
Errata type: Errata
Description: The Shared Time Angle Counter (STAC) bus allows an Enhanced Time Processing Unit
(eTPU) to export its timebase or angle counters to another eTPU as well as to other
peripherals such as the Enhanced Modular Input/Output Subsystem (eMIOS) and Enhanced
Queued Analog-to-Digital Converter (eQADC). If the eTPU clock is configured to be twice the
frequency of those peripherals, the STAC bus will not be able to transfer timebase or angle
information from the eTPUs to the slower peripherals. The timebase/angle export between
eTPUs, however, is still operational in this configuration.
Workaround: Configure the eTPU clock to the same frequency as peripherals if timebase/angle export to
them is required.
e2740: ETPU2: Watchdog Status Register (WDSR) may fail to update on channel
timeout
Errata type: Errata
Description: The Watchdog Status Register (WDSR) contains a single watchdog status bit for each of the
32 eTPU channels per engine. When this bit is set, it indicates that the corresponding channel
encountered a watchdog timeout and was aborted. Under certain conditions the corresponding
bit is not set due to a watchdog timeout, and therefore no indication is available as to which
channel timed out. However, the global exception is indicated correctly on a per engine basis,
and the correct exception is issued to the interrupt controller and may be serviced.
Workaround: The application software should treat any watchdog event as a global eTPU exception and
handle it in the eTPU global exception handler. Additionally, during the global exception
handler the application should check the WDSR and clear any bits that may be set by writing
'1' to that bit.
Mask Set Errata for Mask 3M17W, Rev 13 SEP 2013
Freescale Semiconductor, Inc. 5