Information

e5640: ETPU2: Watchdog timeout may fail in busy length mode
Errata type: Errata
Description: When the Enhanced Time Processing Unit (eTPU) watchdog is programmed for busy length
mode (eTPU Watchdog Timer Register (ETPU_WDTR) Watchdog Mode field (WDM) = 3), a
watchdog timeout will not be detected if all of the conditions below are met:
1- The watchdog timeout occurs at the time slot transition, at the first instruction of a thread, or
at the thread gap. (a thread gap is a 1 microcycle period between threads that service the
same channel).
2- The thread has only one instruction.
3- The eTPU goes idle right after the timed-out thread, or after consecutive single-instruction
threads.
Workaround: Insert a NOP instruction in threads which have only one instruction.
e2382: FLASH: Flash Array Integrity Check
Errata type: Errata
Description: The Flash Array Integrity Check (AIC) which may be enabled during the flash user test (UTest)
mode does not return the expected UMn[MISR] values for some flash PFCRPn[RWSC] read
wait state configurations. For PFCRPn[RWSC] values of 3-6, the UMn[MISR] signature
computation during AIC does not include the data read from the very last address in the
selected address sequence and thus the UMn[MISR] value is not as expected. For
PFCRPn[RWSC] values of 7, the UMn[MISR] signature computation during AIC will not be
correct as well.
Workaround: The Flash Array Integrity Check is correct for PFCRPn[RWSC] values of 0-2. For
PFCRPn[RWSC] values of 3-6, the expected UMn[MISR] values will not include the data read
from the very last address and thus the value expected should be for the data read up to the
2nd-last address in the selected address sequence. For a PFCRPn[RWSC] value of 7, the
Array Integrity Check should not be used at all.
e1312: FLASH: MCR[DONE] bit may be set before high voltage operation completes
when executing a suspend sequence
Errata type: Errata
Description: The program and erase sequence of the flash may be suspended to allow read and program
access to the flash core. An suspend operation is initiated by setting the Erase Suspend
(ESUS) bit or Program Suspend (PSUS) bit in the flash Module Configuration Register (MCR).
Setting a suspend bit causes the flash module to start the sequence which places it in the
suspended state. The user must then wait until the MCR[DONE] bit is set before a read or
program to the flash is initiated, as the high voltage operation needs to be complete to avoid
errors.
However, during normal read to the same partition, following a suspend sequence, (setting
MCR bit and waiting for MCR[DONE] bit to be set) can result in read fails that will return
multiple bit ECC errors. The error is due to the MCR[DONE] bit being set before the internal
high voltage operation is complete.
Mask Set Errata for Mask 3M17W, Rev 13 SEP 2013
6 Freescale Semiconductor, Inc.