Information

c) Any MB (despite of being Tx or Rx) is reconfigured (by writing its CS field) just after the
Intermission field.
d) A new incoming message sent by any external node starts just after the Intermission field.
Workaround: Do not configure the last MB as a Remote Answer (with code "a").
e2424: FlexCAN: switching CAN protocol interface (CPI) to system clock has very
small chance of causing the CPI to enter an indeterminate state
Errata type: Errata
Description: The reset value for the clock source of the CAN protocol interface (CPI) is the oscillator clock.
If the CPI clock source is switched to the system clock while the FlexCAN is not in freeze
mode, then the CPI has a very small chance of entering an indeterminate state.
Workaround: Switch the clock source while the FlexCAN is in a halted state by setting HALT bit in the
FlexCAN Module Configuration Register (CANx_MCR[HALT]=1). If the write to the CAN
Control Register to change the clock source (CANx_CR[CLK_SRC]=1) is done in the same
oscillator clock period as the write to CANx_MCR[HALT], then chance of the CPI entering an
indeterminate state is extremely small. If those writes are done on different oscillator clock
periods, then the corruption is impossible. Even if the writes happen back-to-back, as long as
the system clock to oscillator clock frequency ratio is less than three, then the writes will
happen on different oscillator clock periods.
e1364: FlexRay : Message Buffer Slot Status corrupted after system memory access
timeout or illegal address access
Errata type: Errata
Description: If the system memory read access that retrieves the first message buffer header data from a
FlexRay transmit buffer fails due to a system memory access timeout or illegal address
access, it is possible that the slot status information for the previous slot is written into the
currently used transmit message buffer. In this case, the slot status information is not written
into the message buffer assigned to the last slot.
Thus, both the message buffer assigned to the last slot, and the currently used transmit
message buffer contain incorrect slot status information.
However, if this occurs, either the System Bus Communication Failure Error Flag (SBCF_EF)
or the Illegal System Bus Address Error Flag (ILSA_EF) will be set in the Controller Host
Interface Error Flag Register (CHIERFR).
Workaround: The FlexRay module and the system memory subsystem should be configured to avoid the
occurrence of system memory access timeouts and illegal address accesses.
In case that one of the error flags CHIERFR[SBCF_EF] or CHIERFR[ILSA_EF] is set, the
application should not use the slot status information of the message buffers.
e1369: FlexRay : Message Buffer Status, Slot Status, and Data not updated after
system memory access timeout or illegal address access
Errata type: Errata
Mask Set Errata for Mask 3M17W, Rev 13 SEP 2013
8 Freescale Semiconductor, Inc.