Datasheet

2000 Jul 31 16
NXP Semiconductors Product specification
Low power audio DAC with PLL UDA1334ATS
handbook, full pagewidth
MGL974
47 Ω
R5
UDA1334ATS
6
SYSCLK/PLL1
27 MHz
clock
1
BCK
2
WS
3
DATAI
14
VOUTL
R3
100 Ω
R1
220 kΩ
16
VOUTR
R4
100 Ω
R2
220 kΩ
7
SFOR1
11
SFOR0
9
audio clock
I
2
S-bus
(master)
DEEM/CLKOUT
10
PLL0
8
MUTE
MPEG
DECODER
47 μF
(16 V)
C4
47 μF
(16 V)
C3
left
outp
ut
right
outp
ut
12
V
ref(DAC)
C7
47 μF
(16 V)
C8
100 nF
(63 V)
45
V
DDD
V
SSD
R6
1 Ω
digital
supply voltage
C6
15 13
V
SSA
V
DDA
R7
1 Ω
C9
47 μF
(16 V)
C10
100 nF
(63 V)
100 nF
(63 V)
analog
supply voltage
C5
47 μF
(16 V)
C1
10 nF
(63 V)
10 nF
(63 V)
C2
Fig.9 Video mode application diagram.
In video mode, a clock output signal is generated by the UDA1334ATS which is master for the audio signals in the system; the digital audio interface is
slave, which means the system must generate the BCK and WS signal from the UDA1334ATS output clock.