Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate and inverter NOR gate 7SET TSSOP 5

1. General description

XC7SET02 is a high-speed Si-gate CMOS device. It provides a 2-input NOR function.

2. Features

n Symmetrical output impedance

n High noise immunity

n Low power dissipation

n Balanced propagation delays

n SOT353-1 and SOT753 package options

n ESD protection:

u HBM JESD22-A114E: exceeds 2000 V

u MM JESD22-A115-A: exceeds 200 V

u CDM JESD22-C101C: exceeds 1000 V

n Speciﬁed from −40 °C to +125 °C

3. Ordering information

XC7SET02

2-input NOR gate

Rev. 01 — 31 August 2009 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

XC7SET02GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package;

5 leads; body width 1.25 mm

SOT353-1

XC7SET02GV −40 °C to +125 °C SC-74A plastic surface-mounted package; 5 leads SOT753

Summary of content (11 pages)

PAGE 1
XC7SET02 2-input NOR gate Rev. 01 — 31 August 2009 Product data sheet 1. General description XC7SET02 is a high-speed Si-gate CMOS device. It provides a 2-input NOR function. 2. Features n n n n n n Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays SOT353-1 and SOT753 package options ESD protection: u HBM JESD22-A114E: exceeds 2000 V u MM JESD22-A115-A: exceeds 200 V u CDM JESD22-C101C: exceeds 1000 V n Specified from −40 °C to +125 °C 3.
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XC7SET02 NXP Semiconductors 2-input NOR gate 4. Marking Table 2. Marking codes Type number Marking[1] XC7SET02GW gB XC7SET02GV g02 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram B 1 B 2 A Y 1 4 ≥1 4 Y 2 A mna104 mna103 Fig 1. Logic symbol mna105 Fig 2. IEC logic symbol Fig 3. Logic diagram 6. Pinning information 6.1 Pinning XC7SET02 B 1 A 2 GND 3 5 VCC 4 Y 001aak136 Fig 4.
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XC7SET02 NXP Semiconductors 2-input NOR gate 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level Inputs Output A B Y L L H L H L H L L H H L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Min Max Unit VCC supply voltage Conditions −0.5 +7.0 V VI input voltage −0.5 +7.0 V IIK input clamping current VI < −0.
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XC7SET02 NXP Semiconductors 2-input NOR gate 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit 4.5 5.0 5.5 V VCC supply voltage VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate - - 20 ns/V 10. Static characteristics Table 7.
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XC7SET02 NXP Semiconductors 2-input NOR gate 11. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V. For test circuit see Figure 6. Symbol Parameter propagation delay tpd 25 °C Conditions A and B to Y; see Figure 5 VCC = 4.5 V to 5.5 V [1] per buffer; CL = 50 pF; f = 1 MHz; VI = GND to VCC Typ Max Min Max Min Max - 3.5 5.5 1.0 6.5 1.0 7.0 - 4.9 7.5 1.0 8.5 1.0 9.
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XC7SET02 NXP Semiconductors 2-input NOR gate 12. Waveforms VM A, B input tPHL tPLH VM Y output mna106 Measurement points are given in Table 9. Fig 5. The inputs (A and B) to output (Y) propagation delays Table 9. Measurement point Type Input XC7SET02 Output VI VM VM GND to 3.0 V 1.5 V 0.5 × VCC VCC PULSE GENERATOR VI VO DUT CL RT mna101 Test data is given in Table 10. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance.
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XC7SET02 NXP Semiconductors 2-input NOR gate 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm E D SOT353-1 A X c y HE v M A Z 5 4 A2 A (A3) A1 θ 1 Lp 3 L e w M bp detail X e1 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) θ mm 1.1 0.1 0 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.425 0.46 0.
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XC7SET02 NXP Semiconductors 2-input NOR gate Plastic surface-mounted package; 5 leads SOT753 D E B y A X HE 5 v M A 4 Q A A1 c 1 2 3 Lp detail X bp e w M B 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.100 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.
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XC7SET02 NXP Semiconductors 2-input NOR gate 14. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes XC7SET02_1 20090831 Product data sheet - - XC7SET02_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev.
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XC7SET02 NXP Semiconductors 2-input NOR gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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XC7SET02 NXP Semiconductors 2-input NOR gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . .