Freescale Semiconductor Advance Information Document Number: MC10XSC425 Rev. 2.0, 9/2013 Quad High Side Switch (Dual 10 mOhm, Dual 25 mOhm) 10XSC425 The 10XSC425 is one in a family of devices designed for low-voltage lighting or factory automation applications. Its four low RDS(ON) MOSFETs (dual 10 m/dual 25 m) can control four separate 55 W / 28 W bulbs, and/or Xenon modules, and/or LEDs, and/or DC low voltage motors.
10XSC425 2 Analog Integrated Circuit Device Data Freescale Semiconductor
Table of Contents 1 2 3 Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.6Reverse Battery ON VPWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.7Ground Disconnect Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.8Loss of Supply Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.
1 Orderable Parts This section describes the part numbers available to be purchased along with their differences. Table 1. Orderable Part Variations Part Number (1) Temperature (TA) Package Quad version MC10XSC425EK -40 to 125°C 32 pin SOIC exposed pad Notes 1. To Order parts in Tape & Real, add the R2 suffix to the part number. Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http:// www.freescale.
2 Internal Block Diagram VDD IUP VPWR VDD Failure Detection Internal Regulator POR Over/Undervoltage Protections VPWR Voltage Clamp Charge Pump VREG CSB SCLK Selectable Slew Rate Gate Driver IDWN Selectable Overcurrent Detection SO SI RSTB WAKE FSB IN0 HS0 Severe Short-circuit Detection Logic Short to VPWR Detection Overtemperature Detection IN1 IN2 Open-Load Detections IN3 HS0 RDWN IDWN RDWN HS1 Calibratable Oscillator HS1 PWM Module HS2 VREG HS2 HS3 FSI HS3 Programmable Wa
3 Pin Connections 3.1 Pinout Diagram Transparent Top View of Package WAKE 1 32 FSB RSTB 2 31 IN3 CSB 3 30 IN2 SCLK 4 29 IN1 SI 5 28 IN0 VDD 6 27 CSNS SO 7 26 FSI GND 8 25 GND VPWR 9 24 NC HS3 10 23 HS2 HS3 11 22 HS2 HS3 12 21 HS2 HS3 13 20 HS2 HS1 14 19 HS0 HS1 15 18 HS0 HS1 16 17 HS0 Figure 3. 10XSC425 Pin Connections 3.2 Pin Definitions Table 2.
Table 2. 10XSC425 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 28. Pin Number Pin Name Pin Function Formal Name Definition 8, 25 GND Ground Ground These pins, internally shorted, are the ground for the logic and analog circuitry of the device. These ground pins must be also shorted in the board.
4 Electrical Characteristics 4.1 Maximum Ratings Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Ratings Value Unit Notes ELECTRICAL RATINGS VPWR(SS) VPWR Supply Voltage Range • Load Dump at 25 °C (400 ms) • Maximum Operating Voltage • Reverse Battery V 41 28 -18 VDD VDD Supply Voltage Range -0.3 to 5.5 V VDIG Input / Output Voltage -0.3 to 5.
Table 3. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Ratings Value Unit Notes C (5) THERMAL RATINGS TA TJ TSTG Operating Temperature • Ambient • Junction - 40 to 125 - 40 to 150 Storage Temperature - 55 to 150 C THERMAL RESISTANCE RJC RJA TSOLDER Thermal Resistance • Junction to Case • Junction to Ambient <2.
4.2 Static Electrical Characteristics Table 4. Static Electrical Characteristics Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes V (9) V (10) POWER INPUTS Battery Supply Voltage Range • Fully Operational • Extended mode 6.0 4.
Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max 77.6 46.4 43.6 40.2 31.6 26.2 19.2 12.1 10.3 6.2 101.6 62 55.6 48.8 40.4 33.2 24.3 15.3 13.1 8.3 125.6 77.6 67.6 57.4 49.2 40.2 29.4 18.4 15.9 10.
Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit VDD+0.25 – VDD+1.0 OFF OpenLoad Detection Source Current 30 – 100 A OFF OpenLoad Fault Detection Voltage Threshold 2.0 3.0 4.0 V 2.
Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes OUTPUTS HS0 TO HS3 (CONTINUED) CSR0_x_ACC HS[2,3] Current Sense Ratio (CSR0) Accuracy (6.
Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes 125 250 500 k – 4.
4.3 Dynamic Electrical Characteristics Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max 300 650 1200 300 720 1200 0.8 0.9 1.
Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max 4.40 1.62 2.10 2.88 4.58 10.16 73.2 6.30 2.32 3.00 4.12 6.56 14.52 104.6 8.02 3.00 3.90 5.36 8.54 18.88 134.
Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes Input PWM Clock Range on IN0 7.68 – 30.72 kHz fIN0(LOW) Input PWM Clock Low Frequency Detection Range on IN0 1.0 2.0 4.
Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes SPI INTERFACE CHARACTERISTICS(38) f SPI Maximum Frequency of SPI Operation – – 8.
4.4 Timing Diagrams IN[0:3] High logic level Low logic level Time or CSB High logic level Low logic level Time VHS[0:3] VPWR RPWM 50%VPWR Time t DLY(ON) VHS[0:3] 70% VPWR t DLY(OFF) SR F SR R 30% VPWR Time Figure 4. Output Slew Rate and Time Delays IOCH1 IOCH2 Load Current IOC1 IOC2 IOC3 IOC4 IOCLO4 IOCLO3 IOCLO2 IOCLO1 Time t OC1 t OC2 t OC3 t OC4 t OC5 t OC6 t OC7 Figure 5.
IOCH1 IOCH2 IOC1 IOC2 IOC3 IOC4 IOCLO4 IOCLO3 IOCLO2 IOCLO1 t BC3 tB C1 t BC2 t BC4 tB C5 Previous OFF duration (toff) tB C6 Figure 6. Bulb Cooling Management VIH VIH RSTB RSTB 10% 0.2 VDDVDD tWRSTB TwRSTB tENBL VIL VIL tTCSB CSB TENBL VIH VIH 90% VDD 0.7VDD CSB CSB 10% VDD 0.7VDD t WSCLKH TwSCLKh tTlead LEAD VIL VIL t RSI TrSI t LAG Tlag 90% VDD 0.7VDD SCLK SCLK VIH VIH 10% VDD 0.2VDD t TSIsu SI(SU) VIL VIL t WSCLKl TwSCLKl t SI(HOLD) TSI(hold) SI SI Don’t Care 90% VDD 0.
tFSI tRSI TrSI TfSI VOH VOH 90% VDD 3.5V 50% SCLK SCLK 1.0V VDD 10% VOL VOL t SO(EN) TdlyLH SO SO 90% VDD 0.7 VDD 0.210% VDDVDD VOH VOH VOL VOL Low-to-High Low to High TrSO t RSO VALID tTVALID SO TfSO t FSO SO VOH VOH VDD VDD High to Low 0.790% High-to-Low 0.2VDD 10% VDD TdlyHL VOL VOL t SO(DIS) Figure 8.
5 Functional Description 5.1 Introduction The 10XSC425 is one in a family of devices designed for low-voltage lighting applications. Its four low RDS(ON) MOSFETs (dual 10 m, dual 25 m) can control four separate 55 W / 28 W bulbs and/or Xenon modules. Programming, control, and diagnostics are accomplished using a 16-bit SPI interface. Its output with selectable slew rate improves electromagnetic compatibility (EMC) behavior.
5.2.7 Serial Clock (SCLK) The SCLK pin clocks the internal shift registers of the 10XSC425 device. The serial input (SI) pin accepts data into the input shift register on the falling edge of the SCLK signal, while the serial output (SO) pin shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important the SCLK pin be in a logic low state whenever CSB makes any transition.
5.3 Functional Internal Block Description 10XSC425 - Functional Block Diagram Power Supply MCU Interface & Output Control Self-Protected High Side Switches HS0-HS3 SPI Interface Parallel Control Inputs MCU Interface PWM Controller Supply MCU Interface & Output Control Self-Protected High Side Switches Figure 9. Functional Block Diagram 5.3.1 Power Supply The 10XSC425 is designed to operate from 4.0 to 28 V on the VPWR pin. Characteristics are provided from 6.0 to 20 V for the device.
6 Functional Device Operation 6.1 SPI Protocol Description The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK), and Chip Select (CSB). The SI / SO pins of the 10XSC425 follow a first-in first-out (D15 to D0) protocol, with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 5.0 or 3.3 V CMOS logic levels.
Table 6. 10XSC425 Operating Modes Mode Wake-up Fail Fault Comments Sleep 0 x x Device is in Sleep mode. All outputs are OFF. Normal 1 0 0 Device is currently in Normal mode. Watchdog is active if enabled. Fail-safe 1 1 0 Device is currently in Fail-safe mode due to Watchdog timeout or VDD Failure conditions. The output states are defined with the RFS resistor connected to FSI. Fault 1 X 1 Device is currently in fault mode. The faulted output(s) is (are) OFF.
6.2.2 Normal Mode The 10XSC425 is in Normal mode when: • VPWR and VDD are within the normal voltage range, • wake-up = 1, • fail = 0, • fault = 0. In this mode, the NM bit is set to lfault_contrologic [1] and the outputs HS[0:3] are under control, as defined by hson signal: hson[x] = ( ( (IN[x] and DIR_dis[x]) or On bit[x] ) and PWM_en ) or (On bit [x] and Duty_cycle[x] and PWM_en).
6.2.2.2 Calibratable Internal Clock The internal clock can vary as much as 30%, corresponding to a typical fPWM(0) output switching period. Using the existing SPI inputs and the precision timing reference already available to the MCU, the 10XSC425 allows clock period setting within 10% accuracy. Calibrating the internal clock is initiated by defined word to CALR register. The calibration pulse is provided by the MCU. The pulse is sent on the CSB pin after the SPI word is launched.
6.2.5 6.2.5.1 Normal and Fail-safe Mode Transitions Transition Fail-safe to Normal Mode To leave the Fail-safe mode, VDD must be in nominal voltage and the microcontroller has to send a SPI command with the WDIN bit set to logic [1]; the other bits are not considered. The previous latched faults are reset by the transition into Normal mode (autoretry included). Moreover, the device can be brought out of the Fail-safe mode due to a watchdog timeout issue, by forcing the FSI pin to logic [0]. 6.2.5.
6.3 Protection and Diagnostic Features 6.3.1 Protections 6.3.1.1 Overtemperature Fault The 10XSC425 incorporates overtemperature detection and shutdown circuitry for each output structure. Two cases need to be considered when the output temperature is higher than TSD: • If the output command is ON: the corresponding output is latched OFF. FSB will be also latched to logic [0].
Depending dependingon to toff toff Over-current thresholds Cooling toff hson signal fault_control PWM hson 6.3.1.3 Severe Short-circuit Fault The 10XSC425 provides output shutdown to protect each output, in case of a severe short-circuit during the output switching. If the short-circuit impedance is below RSHORT, the device will latch the output OFF, FSB will go to a logic [0] and the fault register SC[0:3] bit will be set to [1].
(fault_control=0) (OpenLoadOFF = 1 or ShortVpwr = 1 or OV = 1) (fault_control = 1 and OV = 0) OFF if hson = 0 (fault_control = 0 or OV = 1) (OpenLoadOFF = 1 or ShortVpwr = 1 or OV = 1) (OpenLoadON = 1) ON (SC = 1) if hson=1 (Retry = 1) (fault_control = 0) Latched OFF (count = 16) (SC = 1) (OpenloadON = 1) (after Retry Period and OV = 0) Autoretry (OV = 1) OFF Autoretry ON if hson=1 (OpenLoadOFF = 1 or ShortVpwr = 1 or OV = 1) (Retry = 1) => count = count+1 (fault_control=0) Figure 13.
6.3.3.3 OpenLoad Detection In Off State The OFF output OpenLoad fault is detected when the output voltage is higher than VOLD(THRES) pulled up with internal current source (IOLD(OFF)), and reported as a fault condition when the output is disabled (OFF). The OFF Output OpenLoad fault is latched into the status register, or when the internal gate voltage is pulled low enough to turn the output OFF. The OL_OFF[0:3] fault bit is set in the status register.
6.3.7 Ground Disconnect Protection In the event the 10XSC425 ground is disconnected from load ground, the device protects itself and safely turns OFF the output, regardless of the state of the output at the time of disconnection (maximum VPWR = 16 V). A 10 k resistor needs to be added between the MCU and each digital input pin, to ensure that the device turns off during ground disconnects and to prevent this pin from exceeding maximum ratings. 6.3.8 6.3.8.
Multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable, or to confirm transmitted data, as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is not 16 bits will be ignored. The 10XSC425 has defined registers, which are used to configure the device and to control the state of the outputs. Table 11 summarizes the SI registers. Table 10.
6.4.2 Device Register Addressing The following section describes the possible register addresses (D[14:10]) and their impact on device operation. 6.4.2.1 Address XX000 — Status Register (STATR_s) The STATR register is used to read the device status and the various configuration register contents without disrupting the device operation or the register contents. The register bits D[4:0] determine the content of the first sixteen bits of SO data.
6.4.2.4 Address A1A0011 — Output Configuration Register (CONFR1_s) The CONFR1_s register allows the MCU to configure corresponding output fault management through the SPI. Each output “s” is independently selected for configuration, based on the state of the D14 : D13 bits (Table 12). A logic [1] on bit D6 (RETRY_unlimited_s) disables the autoretry counter for the selected output, the default value [1] corresponds to enable auto-retry feature without time limitation.
Xenon bit set to logic [0]: IOCH1 IOCH2 IOC1 IOC2 IOCLO4 IOCLO3 IOCLO2 IOCLO1 t OC1 t OC3 t OC4 t OC5 t OC2 t OC6 Time t OC7 Xenon bit set to logic [1]: IOCH1 IOCH2 IOC1 IOC2 IOC3 IOC4 IOCL4 IOCL3 IOCL2 IOCL1 t OC1 t OC3 t OC4 t OC5 t OC2 t OC6 Time t OC7 Figure 14. Overcurrent Profile Depending on Xenon Bit D[7:6] bits allow to MCU to programmable the bulb cooling curve and D[5:4] bits inrush curve for the selected output, as shown Table 16 and Table 17. Table 16.
IOCH1 IOCH2 IOC1 IOC2 IOC3 IOC4 IOCL4 IOCL3 IOCL2 IOCL1 t OC1 t OC3 t OC4 t OC5 t OC2 t OC6 t OC7 Time Figure 15. Overcurrent Profile with OCHI Bit Set to ‘1’ The wire harness is protected by one of four possible current levels in steady state, as defined in Table 18. Table 18. Output Steady State Selection OCLO1 (D2) OCLO0 (D1) Steady State Current 0 0 OCLO2 (default) 0 1 OCLO3 1 0 OCLO4 1 1 OCLO1 Bit D0 (OC_mode_sel) allows to select the overcurrent mode, as described Table 19.
Table 21. CSNS Reporting Selection TEMP_en (D5) CSNS_en (D4) CSNS reporting 0 0 CSNS tri-stated (default) X 1 current recopy of selected output (D3:2] bits) 1 0 temperature on GND flag Table 22. Output Current Recopy Selection CSNS1 (D3) CSNS0 (D2) CSNS reporting 0 0 HS0 (default) 0 1 HS1 1 0 HS2 1 1 HS3 The GCR register disables the overvoltage protection (D0). When this bits is [0], the overvoltage is enabled (default value). 6.4.2.
6.4.4 Serial Output Bit Assignment The 16 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 23, summarizes SO returned data for bits OD15 : OD0. • Bit OD15 is the MSB; it reflects the state of the Watchdog bit from the previously clocked-in message. • Bits OD14:OD10 reflect the state of the bits SOA4 : SOA0 from the previously clocked-in message. • Bit OD9 is set to logic [1] in Normal mode (NM).
6.4.4.1 Previous Address SOA4 : SOA0 = A1A0000 (STATR_s) The returned data OD8 reports logic [1] in case of previous Power ON Reset condition (VSUPPLY(POR)). This bit is only reset by a read operation. Bits OD7: OD0 reflect the current state of the Fault register (FLTR) corresponding to the output previously selected with the bits SOA4:SOA3 = A1A0 (Table 23).
6.4.4.9 Previous Address SOA4 : SOA0 = 10111 (diagr2) The returned data is the product ID. Bits OD2:OD0 are set to 011 for Protected Dual 10 m and 25 m high side Switches. Default Device configuration The default device configuration is explained by the following: • HS output is commanded by corresponding IN input or On bit through the SPI.
7 Typical Applications 7.1 Introduction The following figure shows a typical lighting application (only one vehicle corner) using an external PWM clock from the main MCU. A redundancy circuitry has been implemented to substitute light control (from MCU to watchdog) in case of a Fail-safe condition. It is recommended to locate a 22 nF decoupling capacitor to the module connector.
8 Packaging 8.1 Soldering Information The 10XSC425 was qualified in accordance with JEDEC standards J-STD-020C Pb-free reflow profile. The maximum peak temperature during the soldering process should not exceed 260 °C for 40 seconds maximum duration. 8.2 Marking Information The device is identified by the part number: 10XSC425. Device markings indicate build information containing the week and year of manufacture.
EK SUFFIX 32-PIN SOIC-EP 98ASA00368D ISSUE 0 10XSC425 52 Analog Integrated Circuit Device Data Freescale Semiconductor
EK SUFFIX 32-PIN SOIC-EP 98ASA00368D ISSUE 0 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 53
EK SUFFIX 32-PIN SOIC-EP 98ASA00368D ISSUE 0 10XSC425 54 Analog Integrated Circuit Device Data Freescale Semiconductor
9 Revision History REVISION 1.0 2.0 DATE 8/2013 9/2013 DESCRIPTION OF CHANGES • Initial release based on the MC10XS3425 data sheet • Added the note “To achieve high reliability over 10 years of continuous operation, the device's continuous operating junction temperature should not exceed 125C.
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