Freescale Semiconductor Advance Information Document Number: MC07XSC200 Rev. 2.0, 9/2013 Dual High Side Switch (7.0 mOhm) 07XSC200 The 07XSC200 is one in a family of devices designed for low-voltage lighting or factory automation applications. Its two low RDS(ON) MOSFETs (dual 7.0 m) can control two separate 55 W / 28 W bulbs, and/or Xenon modules, and/or LEDs, and/or DC low voltage motors. Programming, control and diagnostics are accomplished using a 16-bit SPI interface.
1 Internal Block Diagram VDD IUP VPWR VDD Failure Detection Internal Regulator POR Over/Undervoltage Protections VPWR Voltage Clamp Charge Pump VREG CSB SCLK Selectable Slew Rate Gate Driver IDWN Selectable Overcurrent Detection SO SI RSTB WAKE FSB IN0 HS0 Severe Short-circuit Detection Logic Short to VPWR Detection Overtemperature Detection IN1 CLOCK OpenLoad Detections HS0 RDWN IDWN RDWN HS1 Calibratable Oscillator PWM Module HS1 Overtemperature Prewarning VREG Selectable Outpu
2 Pin Connections 2.1 Pinout Diagram Transparent top View RSTB CSB SCLK SI VDD SO GND VPWR HS1 HS1 HS1 HS1 HS1 HS1 HS1 HS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 VPWR 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 WAKE FSB IN1 IN0 CLOCK CSNS FSI GND HS0 HS0 HS0 HS0 HS0 HS0 HS0 HS0 Figure 3. 07XSC200 Pin Connection 2.2 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 22. Table 1.
Table 1. 07XSC200 Pin Definitions (continued) Pin Number Pin Name Pin Function 8, 33 VPWR Power 9 to 16 HS1 Output High Side Output Protected 7.0 m high side power output pin to the load. Those pins must be shorted at board level. 26 FSI Input Fail-safe Input The value of the resistance connected between this pin and ground determines the state of the outputs after a watchdog time-out occurs.
3 Electrical Characteristics 3.1 Maximum Ratings Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit ELECTRICAL RATINGS VPWR Supply Voltage Range V VPWR(SS) • Load Dump at 25 °C (400 ms) 41 • Maximum Operating Voltage 28 • Reverse Battery -18 VDD Supply Voltage Range VDD -0.3 to 5.5 V (4) -0.3 to VDD + 0.
Table 2. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value • Ambient TA - 40 to 125 • Junction (5) TJ - 40 to 150 Storage Temperature TSTG - 55 to 150 • Junction to Case RJC 4.
3.2 Static Electrical Characteristics Table 3. Static Electrical Characteristics Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max • Fully Operational 6.0 – 20 • Extended mode(8) 4.0 – 28 41 47 53 – 6.
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max • VPWR = 4.5 V – – 25.2 • VPWR = 6.0 V • VPWR = 10 V – – 11.2 – – 7.0 • VPWR = 13 V – – 7.0 • VPWR = 4.5 V – – 42.8 • VPWR = 6.
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit OUTPUTS HS0 TO HS1 (CONTINUED) HS[0,1] Current Sense Ratio (6.0 V < VHS[0:1] < 20 V, CSNS < 5.
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit OUTPUTS HS0 TO HS1 (CONTINUED) HS[0,1] Current Sense Ratio (CSR1) Accuracy (6.
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit VIH 2.0 – VDD+0.3 V VIL -0.3 – 0.8 V IDWN 5.0 – 20 A IUP 5.0 – 20 A CSO – – 20 pF RDWN 125 250 500 k CIN – 4.
3.3 Dynamic Electrical Characteristics Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max 0.15 0.3 0.6 0.07 0.15 0.3 0.3 0.6 1.2 0.15 0.3 0.6 0.07 0.15 0.3 0.3 0.6 1.
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit Fault Detection Blanking Time(28) tFAULT 1.0 5.0 20 s Time(29) tDETECT – 7.
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max tOC1_00 4.40 6.30 8.02 tOC2_00 1.62 2.32 3.00 tOC3_00 2.10 3.00 3.90 tOC4_00 2.88 4.12 5.36 tOC5_00 4.58 6.56 8.54 tOC6_00 10.16 14.
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max tOC1_00 3.4 4.9 6.4 tOC2_00 1.1 1.6 2.1 tOC3_00 1.4 2.1 2.8 tOC4_00 2.0 2.9 3.8 tOC5_00 3.4 4.9 6.4 tOC6_00 8.5 12.2 15.
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted.
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit PWM MODULE TIMING Input PWM Clock Range on CLOCK Input PWM Clock Low Frequency Detection Range on fCLOCK 7.68 – 30.
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit f SPI – – 8.
3.4 Timing Diagrams IN[0:1] High logic level Low logic level Time or CSB High logic level Low logic level Time VHS[0:1] VPWR RPWM 50%VPWR Time t DLY(ON) VHS[0:1] 70% VPWR t DLY(OFF) SR F SR R 30% VPWR Time Figure 4. Output Slew Rate and Time Delays IOCH1 IOCH2 Load Current IOC1 IOC2 IOC3 IOC4 IOCLO4 IOCLO3 IOCLO2 IOCLO1 Time t OC1 t OC2 t OC3 t OC4 t OC5 t OC6 t OC7 Figure 5.
IOCH1 IOCH2 IOC1 IOC2 IOC3 IOC4 IOCLO4 IOCLO3 IOCLO2 IOCLO1 t BC3 tB C1 t BC2 t BC4 tB C5 Previous OFF duration (tOFF) tB C6 Figure 6. Bulb Cooling Management VIH VIH RSTB RSTB 10% 0.2 VDDVDD tWRSTB VIL VIL TwRSTB tENBL TCSB t CSB TENBL VIH VIH 90% VDD 0.7VDD CSB CSB 0.7VDD 10% VDD t WSCLKH TwSCLKh tTlead LEAD VIL VIL t RSI TrSI t LAG 90% VDD 0.7VDD SCLK SCLK Tlag VIH VIH 10% VDD 0.2VDD VIL VIL t SI(SU) TSIsu SI SI Don’t Care 90% 0.7 VDD VDD 0.
tFSI tRSI TrSI TfSI VOH VOH 90% VDD 3.5V 50% SCLK SCLK 1.0V VDD 10% VOL VOL t SO(EN) TdlyLH SO SO 90% VDD 0.7 VDD 0.210% VDDVDD VOH VOH VOL VOL Low-to-High Low to High TrSO t RSO VALID tTVALID SO TfSO t FSO SO VOH VOH VDD VDD High to Low 0.790% High-to-Low 0.2VDD 10% VDD TdlyHL VOL VOL t SO(DIS) Figure 8.
4 Functional Description 4.1 Introduction The 07XSC200 is one in a family of devices designed for low-voltage lighting applications. Its two low RDS(ON) MOSFETs (dual 7.0 m) can control two separate 55 W / 28 W bulbs and/or Xenon modules. Programming, control and diagnostics are accomplished using a 16-bit SPI interface. Its output with selectable slew rate improves electromagnetic compatibility (EMC) behavior.
4.2.7 Chip Select (CSB) The CSB pin enables communication with the master microcontroller (MCU). When this pin is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the MCU. The 07XSC200 latches in data from the Input Shift registers to the addressed registers on the rising edge of CSB. The device transfers status information from the power output to the Shift register on the falling edge of CSB.
4.2.15 Fail-safe Input (FSI) This pin incorporates an active internal pull-up current source from internal supply (VREG). This enables the watchdog time-out feature. When the FSI pin is opened, the watchdog circuit is enabled. After a watchdog time-out occurs, the output states depends on IN[0:1]. When the FSI pin is connected to GND, the watchdog circuit is disabled.
4.3.3 MCU Interface and Output Control In Normal mode, each bulb is controlled directly from the MCU through the SPI. A pulse width modulation control module allows improvement of lamp lifetime with bulb power regulation (PWM frequency range from 100 to 400 Hz) and addressing the dimming application (day running light). An analog feedback output provides a current proportional to the load current or the temperature of the board.
5 Functional Device Operation 5.1 SPI Protocol Description The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK), and Chip Select (CSB). The SI / SO pins of the 07XSC200 follow a first-in first-out (D15 to D0) protocol, with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 5.0 or 3.3 V CMOS logic levels.
Table 5. 07XSC200 Operating Modes Mode wake-up fail fault Comments Sleep 0 x x Device is in Sleep mode. All outputs are OFF. Normal 1 0 0 Device is currently in Normal mode. Watchdog is active if enabled. Fail-safe 1 1 0 Device is currently in Fail-safe mode due to watchdog time-out or VDD Failure conditions. The output states are defined with the RFS resistor connected to FSI. Fault 1 X 1 Device is currently in fault mode. The faulted output(s) is (are) OFF.
To avoid this unexpected current leakage on the VDD supply pin, maintain the device in Normal mode with RSTB pin set to logic[1]. This will allow diagnosis of the battery disconnection event through UV fault reporting in SPI. Then, apply 0 V on the VDD supply pin to switch the device to Sleep state. 5.2.2 Normal Mode The 07XSC200 is in Normal mode when: • VPWR and VDD are within the normal voltage range, • wake-up = 1, • fail = 0, • fault = 0.
The clock frequency from CLOCK is permanently monitored in order to report a clock failure in case the frequency is out a specified frequency range (from fCLOCK(LOW) to fCLOCK(HIGH)). In case of clock failure, no PWM feature is provided, the On bit defines the outputs state and the CLOCK_fail bit reports [1]. 5.2.2.2 Calibratable Internal Clock The internal clock can vary as much as 30 percent corresponding to typical fPWM(0) output switching period.
Table 8. SPI Watchdog Activation Typical RFSI () Watchdog 0 (shorted to ground) Disabled (open) Enable During the Fail-safe mode, the outputs will depend on the corresponding input. The SPI register content is reset to their default value (except POR bit) and fault protections are fully operational. The Fail-safe mode can be detected by monitoring the NM bit is set to [0]. 5.2.
• apply PWM clock on CLOCK input pin after maximum 200s (min. 50s). If the correct start-up sequence is not provided, the PWM function is not guaranteed. 5.3 Protection and Diagnostic Features 5.3.1 Protections Over-temperature Fault The 07XSC200 incorporates over-temperature detection and shutdown circuitry for each output structure. Two cases need to be considered when the output temperature is higher than TSD: • If the output command is ON: the corresponding output is latched OFF.
Depending on toff depending to toff Over-current thresholds Cooling toff fault_control hson signal hson PWM 5.3.1.2 Severe Short-circuit Fault The 07XSC200 provides output shutdown to protect each output in case of a severe short-circuit during of the output switching. If the short-circuit impedance is below RSHORT, the device will latch the output OFF, FSB will go to logic [0] and the fault register SC[0:1] bit will be set to [1].
(fault_control=0) (OpenloadOFF=1 or ShortVpwr=1 or OV=1) (fault_control=1 and OV=0) OFF if hson=0 ON (fault_control=0 or OV=1) (fault_control=0) (OpenloadOFF=1 or ShortVpwr=1 or OV=1) (OpenloadON=1) (SC=1) if hson=1 (Retry=1) Latched OFF (count=16) (SC=1) (OpenloadON=1) (after Retry Period and OV=0) Auto-retry (OV=1) OFF Auto-retry ON if hson=1 (OpenloadOFF=1 or ShortVpwr=1 or OV=1) (Retry=1) => count=count+1 (fault_control=0) Figure 13. Auto-retry State Machine 5.3.
5.3.3.1 OpenLoad Detection in Off State The OFF output OpenLoad fault is detected when the output voltage is higher than VOLD(THRES) pulled up with internal current source (IOLD(OFF)) and reported as a fault condition when the output is disabled (OFF). The OFF Output OpenLoad fault is latched into the status register or when the internal gate voltage is pulled low enough to turn OFF the output. The OL_OFF[0:1] fault bit is set in the status register.
5.3.6 Ground Disconnect Protection In the event the 07XSC200 ground is disconnected from load ground, the device protects itself and safely turns OFF the output, regardless of the state of the output at the time of disconnection (maximum VPWR = 16 V). A 10 k resistor needs to be added between the MCU and each digital input pin to ensure the device turns off, during a ground disconnect and to prevent this pin from exceeding maximum ratings. 5.3.7 5.3.7.
Table 9. SI Message Bit Assignment Bit Sig SI Msg Bit Message Bit Description MSB D15 Watchdog in: toggled to satisfy watchdog requirements. D13 Register address bit used in some cases for output selection (Table 11). D14, D12 : D10 Not used (set to logic [0]). D9 LSB Register address bits. Used to configure the inputs, outputs, and the device protection features and SO status content. D8:D0 Table 10.
5.4.2 Device Register Addressing The following section describes the possible register addresses (D[14:10]) and their impact on device operation. 5.4.2.1 Address XX000 — Status Register (STATR_s) The STATR register is used to read the device status and the various configuration register contents without disrupting the device operation or the register contents. The register bits D[4:0] determine the content of the first sixteen bits of SO data.
A logic [1] on bit D5 (RETRY_dis_s) disables the auto-retry for the selected output, the default value [0] corresponds to enable this feature. A logic [1] on bit D4 (OS_dis_s) disables the output hard shorted to VPWR protection for the selected output, the default value [0] corresponds to enable this feature. A logic [1] on bit D3 (OLON_dis_s) disables the ON output OpenLoad detection for the selected output, the default value [0] corresponds to enable this feature (Table 13).
Xenon bit set to logic [0]: IOCH1 IOCH2 IOC1 IOC2 IOCLO4 IOCLO3 IOCLO2 IOCLO1 t OC1 t OC3 t OC4 t OC5 t OC2 t OC6 Time t OC7 Xenon bit set to logic [1]: IOCH1 IOCH2 IOC1 IOC2 IOC3 IOC4 IOCL4 IOCL3 IOCL2 IOCL1 t OC1 t OC3 t OC4 t OC5 t OC2 t OC6 Time t OC7 Figure 14. Overcurrent Profile Depending on Xenon bit D[7:6] bits allow to MCU to programmable bulb cooling curve and D[5:4] bits inrush curve for selected output, as shown Table 15 and Table 16. Table 15.
IOCH1 IOCH2 IOC1 IOC2 IOC3 IOC4 IOCL4 IOCL3 IOCL2 IOCL1 t OC1 t OC3 t OC4 t OC5 t OC2 t OC6 t OC7 Time Figure 15. Overcurrent Profile with OCHI bit set to ‘1’ The wire harness is protected by one of four possible current levels in steady state, as defined in Table 17. Table 17. Output Steady State Selection OCLO1 (D2) OCLO0 (D1) Steady State Current 0 0 OCLO2 (default) 0 1 OCLO3 1 0 OCLO4 1 1 OCLO1 Bit D0 (OC_mode_sel) allows to select the overcurrent mode, as described Table 18.
Table 20. CSNS Reporting Selection TEMP_en (D5) CSNS_en (D4) CSNS reporting 0 0 CSNS tri-stated (default) X 1 current recopy of selected output (D3:2] bits) 1 0 temperature on GND flag Table 21. Output Current Recopy Selection CSNS1 (D3) CSNS0 (D2) CSNS reporting 1 0 HS0 1 1 HS1 The GCR register disables the overvoltage protection (D0). When this bits is [0], the overvoltage is enabled (default value). 5.4.2.
Table 22.
• OLON_s: OpenLoad in ON state fault detection (depending on current level threshold: bulb or LED) for a selected output, • OV: overvoltage fault detection, • UV: undervoltage fault detection • POR: power on reset detection. The FSB pin reports all faults. For latched faults, this pin is reset by a new Switch OFF command (toggling fault_control signal). 5.4.4.
5.4.4.10 Default Device Configuration The default device configuration is explained by the following: • HS output is commanded by the corresponding IN input or On bit through the SPI. The medium slew-rate is used, • HS output is fully protected by the Xenon overcurrent profile by default, the severe short-circuit protection, the undervoltage and the overtemperature protection.
6 Typical Applications The following figure shows a typical lighting application (only one vehicle corner) using an external PWM clock from the main MCU. A redundancy circuitry has been implemented to substitute light control (from MCU to watchdog) in case of a Fail-safe condition. It is recommended to locate a 22 nF decoupling capacitor to the module connector.
7 Packaging 7.1 Soldering Information The 07XSC200 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board. The 07XSC200 was qualified in accordance with JEDEC standards J-STD-020C Pb-Free reflow profile. The maximum peak temperature during the soldering process should not exceed 260 °C for 40 seconds maximum duration.
7.2 Package Dimensions Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing’s document number. Package Suffix 32-Pin SOICW EK Package Outline Drawing Number 98ASA00368D EK SUFFIX 32-PIN SOICW 98ASA00368D REV.
EK SUFFIX 32-PIN SOICW 98ASA00368D REV.
EK SUFFIX 32-PIN SOICW 98ASA00368D REV.
8 Revision History Revision Date Description of Changes 1.0 8/2013 • Initial release based on MC07XS3200 data sheet. 2.0 9/2013 • Added the note “To achieve high reliability over 10 years of continuous operation, the device's continuous operating junction temperature should not exceed 125C.
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