MC68HC908GP20 Advance Information M68HC08 Microcontrollers Rev. 2.1 MC68HC908GP20/D 08/2005 freescale.
Advance Information — MC68HC908GP20 List of Sections Section 1. General Description . . . . . . . . . . . . . . . . . . . 31 Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . 43 Section 3. Low-Power Modes . . . . . . . . . . . . . . . . . . . . . 57 Section 4. Resets and Interrupts . . . . . . . . . . . . . . . . . . . 69 Section 5. Analog-to-Digital Converter (ADC) . . . . . . . 87 Section 6. Break Module (BRK). . . . . . . . . . . . . . . . . . . . 99 Section 7.
List of Sections Section 19. System Integration Module (SIM) . . . . . . . 287 Section 20. Serial Peripheral Interface Module (SPI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Section 21. Timebase Module (TBM) . . . . . . . . . . . . . . 345 Section 22. Timer Interface Module (TIM) . . . . . . . . . . 351 Section 23. Preliminary Electrical Specifications . . . . 377 Section 24. Mechanical Specifications . . . . . . . . . . . . 399 Section 25. Ordering Information. . . . . . . . . . . . . .
Advance Information — MC68HC908GP20 Table of Contents Section 1. General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.3.1 Standard Features of the MC68HC908GP20 . . . . . . . . . . . 32 1.3.2 Features of the CPU08 . . . . . . . . . . . . .
Section 2. Memory Map 2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . 43 2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Section 3.
3.10 Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . . 63 3.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.11 Serial Communications Interface Module (SCI) . . . . . . . . . . . . 63 3.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . .
4.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 4.4.1 Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.4.2 Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.4.2.1 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.4.2.2 Break Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.4.2.3 IRQ Pin . . . . . . . .
5.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.7.1 ADC Analog Power Pin (VDDAD)/ADC Voltage Reference High Pin (VREFH) . . . . . . . . . . . . . . . . . . . . .92 5.7.2 ADC Analog Ground Pin (VSSAD)/ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . . . . . . . . . . 92 5.7.3 ADC Voltage In (ADVIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 7. Clock Generator Module (CGMC) 7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 7.4.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . .
7.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 7.8.3 CGMC During Break Interrupts . . . . . . . . . . . . . . . . . . . . . 134 7.9 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 135 7.9.1 Acquisition/Lock Time Definitions . . . . . . . . . . . . .
9.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . 150 Section 10. Central Processor Unit (CPU) 10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 10.
11.6 FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.7 FLASH Program/Margin Read Operation . . . . . . . . . . . . . . . . 177 11.8 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 11.9 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . 181 11.10 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.11 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . .
Section 14. Low-Voltage Inhibit (LVI) 14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 14.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . .
Section 16. Input/Output (I/O) Ports 16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 16.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 16.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 16.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . .
Section 18. Serial Communications Interface Module (SCI) 18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 18.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 18.5 Functional Description . . . . . . . . . . . . . . .
18.9.4 18.9.5 18.9.6 18.9.7 SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Section 19. System Integration Module (SIM) 19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 19.
19.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 19.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 19.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 19.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 19.8.1 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . 308 19.8.2 SIM Reset Status Register . . . . . . . .
20.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 20.13.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . .335 20.13.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . .335 20.13.3 SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 20.13.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 20.13.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . .
22.5.5 22.5.6 22.5.7 22.5.8 22.5.9 22.6 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . 359 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . 359 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . 360 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . 361 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.13 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 23.14 5.0-V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 23.15 3.0-V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 23.16 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . 396 23.17 Clock Generation Module Characteristics . . . . . . . . . . . . . . . 396 23.17.1 CGM Component Specifications . . . . . . . . . . . . . . . . .
Advance Information 22 MC68HC908GP20 — Rev 2.
Advance Information — MC68HC908GP20 List of Figures Figure Page 1-1 1-2 1-3 1-4 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2-1 2-2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figures Figure Advance Information 24 Title Page 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 CGMC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 CGMC External Connections . . . . . . . . . . . . . . . . . . . . . . . 121 CGMC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . 124 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . 125 PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . .
List of Figures Figure Page 14-1 14-2 14-3 LVI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . 201 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 201 LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . 203 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 Monitor Mode Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Low-Voltage Monitor Mode Entry Flowchart . . . . . . . . . . . 211 Monitor Data Format . . . . . . . . .
List of Figures Figure Advance Information 26 Title Page 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 18-14 18-15 18-16 SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . .259 Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . .260 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Fast Data . . . . . . . . . . . . . . . . . . .
List of Figures Figure Page 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 315 SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 316 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . 317 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . 321 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figures Figure 23-1 23-2 23-3 23-4 23-5 23-6 23-7 23-8 23-9 23-10 23-11 Advance Information 28 Title Page Typical High-Side Driver Characteristics – Ports PTA7–PTA0, PTB7–PTB0, PTC6–PTC5, PTD7–PTD0, and PTE1–PTE0 (VDD = 4.5 Vdc). . . . . . 386 Typical High-Side Driver Characteristics – Ports PTA7–PTA0, PTB7–PTB0, PTC6–PTC5, PTD7–PTD0, and PTE1–PTE0 (VDD = 2.7 Vdc). . . . . .
Advance Information — MC68HC908GP20 List of Tables Table Page 2-1 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4-1 4-2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Interrupt Source Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5-1 5-2 Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables Table Advance Information 30 Title Page 16-1 16-2 16-3 16-4 16-5 16-6 Port Control Register Bits Summary . . . . . . . . . . . . . . . . . . 224 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advance Information — MC68HC908GP20 Section 1. General Description 1.1 Contents 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.3.1 Standard Features of the MC68HC908GP20 . . . . . . . . . . . 32 1.3.2 Features of the CPU08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Introduction The MC68HC908GP20 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 1.3 Features For convenience, features have been organized to reflect: • Standard features of the MC68HC908GP20 • Features of the CPU08 1.3.
MC68HC908GP20 — Rev 2.
• Oscillator stop mode enable bit (OSCSTOPENB) in the CONFIG register to allow user selection of having the oscillator enabled or disabled during stop mode • 8-bit keyboard wakeup port • 5-mA maximum current injection on all port pins to maintain input protection • 40-pin plastic dual-in-line package (DIP) or 44-pin quad flat pack (QFP) • Specific features of the MC68HC908GP20 in 40-pin DIP are: – Port C is only 5 bits: PTC0–PTC4 – Port D is only 6 bits: PTD0–PTD5; single 2-channel TIM module 1.3.
USER RAM — 512 BYTES PORTA PORTB DUAL V.
1.
34 PTA2/KBD2 PTA3/KBD3 PTA6/KBD6 38 35 PTA7/KBD7 39 PTA4/KBD4 VDDA 40 36 VSSA 41 PTA5/KBD5 CGMXFC 42 37 OSC2 43 44 OSC1 RST 1 33 PTA1/KBD1 28 PTB6/AD6 PTC5 7 27 PTB5/AD5 PTC6 8 26 PTB4/AD4 PTE0/TxD 9 25 PTB3/AD3 PTE1/RxD 10 24 PTB2/AD2 23 PTB1/AD1 PTB0/AD0 22 PTD0/SS 12 IRQ 11 21 6 PTD7/T2CH1 PTC4 20 PTB7/AD7 PTD6/T2CH0 29 19 5 PTD5/T1CH1 PTC3 18 VDDAD/VREFH PTD4/T1CH0 30 17 4 VDD PTC2 16 VSSAD/VREFL VSS 31 15 3 PTD3/SPSCK PTC1 14 PTA0/KBD0 P
Use a high-frequency-response ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. MCU VSS VDD C1 0.1 µF + C2 VDD NOTE: Component values shown represent typical applications. Figure 1-4. Power Supply Bypassing 1.6.2 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. See Section 7. Clock Generator Module (CGMC). 1.6.
1.6.4 External Interrupt Pin (IRQ) IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor. See Section 12. External Interrupt (IRQ). 1.6.5 CGM Power Supply Pins (VDDA and VSSA) VDDA and VSSA are the power supply pins for the analog portion of the clock generator module (CGM). Decoupling of these pins should be as per the digital supply. See Section 7. Clock Generator Module (CGMC). 1.6.
1.6.10 Port A Input/Output (I/O) Pins (PTA7/KBD7–PTA0/KBD0) PTA7–PTA0 are general-purpose, bidirectional I/O port pins. Any or all of the port A pins can be programmed to serve as keyboard interrupt pins. See Section 16. Input/Output (I/O) Ports and Section 13. Keyboard Interrupt Module (KBI). These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis. 1.6.
These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis. 1.6.14 Port E I/O Pins (PTE1/RxD–PTE0/TxD) PTE0–PTE1 are general-purpose, bidirectional I/O port pins. These pins can also be programmed to be serial communications interface (SCI) pins. See Section 18. Serial Communications Interface Module (SCI) and Section 16. Input/Output (I/O) Ports.
Advance Information 42 MC68HC908GP20 — Rev 2.
Advance Information — MC68HC908GP20 Section 2. Memory Map 2.1 Contents 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . 43 2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.2 Introduction The CPU08 can address 64 Kbytes of memory space.
2.4 Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation. In the Figure 2-1 and in register figures in this document, reserved locations are marked with the word Reserved or with the letter R. 2.5 Input/Output (I/O) Section Most of the control, status, and data registers are in the zero page area of $0000–$003F.
$0000 I/O Registers 64 Bytes ↓ $003F $0040 RAM 512 Bytes ↓ $023F $0240 Unimplemented 44,480 Bytes ↓ $AFFF $B000 FLASH Memory 19,968 Bytes ↓ $FDFF $FE00 SIM Break Status Register (SBSR) $FE01 SIM Reset Status Register (SRSR) $FE02 Reserved (SUBAR) $FE03 SIM Break Flag Control Register (SBFCR) $FE04 Interrupt Status Register 1 (INT1) $FE05 Interrupt Status Register 2 (INT2) $FE06 Interrupt Status Register 3 (INT3) $FE07 Reserved (FLTCR) $FE08 FLASH Control Register (FLCR) $FE09 Break
$FE10 ↓ $FE1F $FE20 ↓ Unimplemented 16 Bytes Reserved for Compatibility with Monitor Code for A-Family Parts Monitor ROM 307 Bytes $FF52 $FF53 ↓ Unimplemented 45 Bytes $FF7F $FF80 FLASH Block Protect Register (FLBPR) $FF81 ↓ Unimplemented 91 Bytes $FFDB Note: $FFF6–$FFFD reserved for 8 security bytes $FFDC ↓ FLASH Vectors 36 Bytes $FFFF Figure 2-1. Memory Map (Continued) Advance Information 46 MC68HC908GP20 — Rev 2.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
. Table 2-1. Vector Addresses Vector Priority Lowest Vector IF16 IF15 IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 IF6 IF5 IF4 IF3 IF2 IF1 — Highest MC68HC908GP20 — Rev 2.
Advance Information 56 MC68HC908GP20 — Rev 2.
Advance Information — MC68HC908GP20 Section 3. Low-Power Modes 3.1 Contents 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.2.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.2.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.3 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . 59 3.3.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . .
3.11 Serial Communications Interface Module (SCI) . . . . . . . . . . . . 63 3.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.12 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . 64 3.12.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.12.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Stop Mode Stop mode is entered when a STOP instruction is executed. The CPU clock is disabled and the bus clock is disabled if the OSCSTOPENB bit in the CONFIG register is at a logic 0. (See Section 8. Configuration Register (CONFIG).) 3.3 Analog-to-Digital Converter (ADC) 3.3.1 Wait Mode The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode.
3.4.2 Stop Mode The break module is inactive in stop mode. A break interrupt causes exit from stop mode and sets the BW bit in the break status register. The STOP instruction does not affect break module register states. 3.5 Central Processor Unit (CPU) 3.5.1 Wait Mode The WAIT instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
applications can disengage the PLL without turning it off. Applications that require the PLL to wake the MCU from wait mode also can deselect the PLL output without turning off the PLL. 3.6.2 Stop Mode If the OSCSTOPEN bit in the CONFIG register is cleared (default), then the STOP instruction disables the CGM (oscillator and phase-locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT).
The STOP bit in the configuration register (CONFIG) enables the STOP instruction. To prevent inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit. 3.8 External Interrupt Module (IRQ) 3.8.1 Wait Mode The IRQ module remains active in wait mode. Clearing the IMASK1 bit in the IRQ status and control register enables IRQ CPU interrupt requests to bring the MCU out of wait mode. 3.8.2 Stop Mode The IRQ module remains active in stop mode.
3.10 Low-Voltage Inhibit Module (LVI) 3.10.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 3.10.2 Stop Mode If enabled, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. 3.11 Serial Communications Interface Module (SCI) 3.11.1 Wait Mode The SCI module remains active in wait mode.
3.12 Serial Peripheral Interface Module (SPI) 3.12.1 Wait Mode The SPI module remains active in wait mode. Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode. If SPI module functions are not required during wait mode, reduce power consumption by disabling the SPI module before executing the WAIT instruction. 3.12.2 Stop Mode The SPI module is inactive in stop mode. The STOP instruction does not affect SPI register states.
3.14 Timebase Module (TBM) 3.14.1 Wait Mode The timebase module remains active after execution of the WAIT instruction. In wait mode, the timebase register is not accessible by the CPU. If the timebase functions are not required during wait mode, reduce the power consumption by stopping the timebase before enabling the WAIT instruction. 3.14.
Advance Information 66 • External interrupt — A high-to-low transition on an external interrupt pin (IRQ pin) loads the program counter with the contents of locations: $FFFA and $FFFB; IRQ pin. • Break interrupt — A break interrupt loads the program counter with the contents of $FFFC and $FFFD. • Computer operating properly module (COP) reset — A timeout of the COP counter resets the MCU and loads the program counter with the contents of $FFFE and $FFFF.
• Serial communications interface module (SCI) interrupt — A CPU interrupt request from the SCI loads the program counter with the contents of: – $FFE2 and $FFE3; SCI transmitter – $FFE4 and $FFE5; SCI receiver – $FFE6 and $FFE7; SCI receiver error • Analog-to-digital converter module (ADC) interrupt — A CPU interrupt request from the ADC loads the program counter with the contents of: $FFDE and $FFDF; ADC conversion complete.
Upon exit from stop mode, the system clocks begin running after an oscillator stabilization delay. A 12-bit stop recovery counter inhibits the system clocks for 4096 CGMXCLK cycles after the reset or external interrupt. The short stop recovery bit, SSREC, in the configuration register controls the oscillator stabilization delay during stop recovery. Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32 CGMXCLK cycles.
Advance Information — MC68HC908GP20 Section 4. Resets and Interrupts 4.1 Contents 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.1 Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.2 External Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4.3.3 Internal Reset . . . . . . .
4.2 Introduction Resets and interrupts are responses to exceptional events during program execution. A reset re-initializes the MCU to its startup condition. An interrupt vectors the program counter to a service routine. 4.3 Resets A reset immediately returns the MCU to a known startup condition and begins program execution from a user-defined memory location. 4.3.
4.3.3 Internal Reset Sources: • Power-on reset (POR) • Computer operating properly (COP) • Low-power reset circuits • Illegal opcode • Illegal address All internal reset sources pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external devices. The MCU is held in reset for an additional 32 CGMXCLK cycles after releasing the RST pin. PULLED LOW BY MCU RST PIN 32 CYCLES 32 CYCLES CGMXCLK INTERNAL RESET Figure 4-1. Internal Reset Timing MC68HC908GP20 — Rev 2.
4.3.3.1 Power-On Reset A power-on reset (POR) is an internal reset caused by a positive transition on the VDD pin. VDD at the POR must go completely to 0 V to reset the MCU. This distinguishes between a reset and a POR. The POR is not a brown-out detector, low-voltage detector, or glitch detector.
4.3.3.2 COP Reset A COP reset is an internal reset caused by an overflow of the COP counter. A COP reset sets the COP bit in the system integration module (SIM) reset status register. To clear the COP counter and prevent a COP reset, write any value to the COP control register at location $FFFF. 4.3.3.3 Low-Voltage Inhibit Reset A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in the power supply voltage to the LVItripf voltage.
4.3.3.5 Illegal Address Reset An illegal address reset is an internal reset caused by opcode fetch from an unmapped address. An illegal address reset sets the ILAD bit in the SIM reset status register. A data fetch from an unmapped address does not generate a reset. 4.3.4 SIM Reset Status Register This read-only register contains flags to show reset sources. All flag bits are automatically cleared following a read of the register.
PIN — External Reset Flag 1 = External reset via RST pin since last read of SRSR 0 = POR or read of SRSR since last external reset COP — Computer Operating Properly Reset Bit 1 = Last reset caused by timeout of COP counter 0 = POR or read of SRSR ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD — Illegal Address Reset Bit 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last
• • • 5 4 CONDITION CODE REGISTER 1 ACCUMULATOR 2 INDEX REGISTER (LOW BYTE)* STACKING 3 ORDER 2 PROGRAM COUNTER (HIGH BYTE) 3 UNSTACKING ORDER 4 1 PROGRAM COUNTER (LOW BYTE) 5 • • • $00FF DEFAULT ADDRESS ON RESET *High byte of index register is not stacked. Figure 4-4. Interrupt Stacking Order After every instruction, the CPU checks all pending interrupts if the I bit is not set.
CLI BACKGROUND ROUTINE LDA #$FF INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 4-5. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE: To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry.
FROM RESET BREAK INTERRUPT ? NO YES YES BIT SET? SET? II BIT NO IRQ INTERRUPT ? NO YES CGM INTERRUPT ? NO YES OTHER INTERRUPTS ? YES NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION ? NO RTI YES INSTRUCTION ? UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 4-6. Interrupt Processing Advance Information 78 MC68HC908GP20 — Rev 2.
4.4.2 Sources The sources in Table 4-1 can generate CPU interrupt requests.
4.4.2.1 SWI Instruction The software interrupt instruction (SWI) causes a non-maskable interrupt. NOTE: A software interrupt pushes PC onto the stack. An SWI does not push PC – 1, as a hardware interrupt does. 4.4.2.2 Break Interrupt The break module causes the CPU to execute an SWI instruction at a software-programmable break point. 4.4.2.3 IRQ Pin A logic 0 on the IRQ1 pin latches an external interrupt request. 4.4.2.
4.4.2.6 TIM2 TIM2 CPU interrupt sources: • TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2 counter value rolls over to $0000 after matching the value in the TIM2 counter modulo registers. The TIM2 overflow interrupt enable bit, TOIE, enables TIM2 overflow CPU interrupt requests. TOF and TOIE are in the TIM2 status and control register. • TIM2 channel flags (CH1F–CH0F) — The CHxF bit is set when an input capture or output compare occurs on channel x.
• Overflow bit (OVRF) — The OVRF bit is set if software does not read the byte in the receive data register before the next full byte enters the shift register. The error interrupt enable bit, ERRIE, enables OVRF CPU interrupt requests. OVRF and ERRIE are in the SPI status and control register. 4.4.2.8 SCI SCI CPU interrupt sources: Advance Information 82 • SCI transmitter empty bit (SCTE) — SCTE is set when the SCI data register transfers a character to the transmit shift register.
• Noise flag (NF) — NF is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, enables NF to generate SCI error CPU interrupt requests. NF is in SCI status register 1. NEIE is in SCI control register 3. • Framing error bit (FE) — FE is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, enables FE to generate SCI error CPU interrupt requests.
4.4.3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 4-2 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging. Table 4-2.
4.4.3.1 Interrupt Status Register 1 Address: $FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 4-7. Interrupt Status Register 1 (INT1) IF6–IF1 — Interrupt Flags 6–1 These flags indicate the presence of interrupt requests from the sources shown in Table 4-2. 1 = Interrupt request present 0 = No interrupt request present Bit 1 and Bit 0 — Always read 0 4.4.3.
4.4.3.3 Interrupt Status Register 3 Address: $FE06 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 IF16 IF15 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 4-9. Interrupt Status Register 3 (INT3) IF16–IF15 — Interrupt Flags 16–15 This flag indicates the presence of an interrupt request from the source shown in Table 4-2. 1 = Interrupt request present 0 = No interrupt request present Bits 7–2 — Always read 0 Advance Information 86 MC68HC908GP20 — Rev 2.
Advance Information — MC68HC908GP20 Section 5. Analog-to-Digital Converter (ADC) 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 5.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.4.2 Voltage Conversion . . .
5.2 Introduction This section describes the 8-bit analog-to-digital converter (ADC). 5.3 Features Features of the ADC module include: • Eight channels with multiplexed input • Linear successive approximation with monotonicity • 8-bit resolution • Single or continuous conversion • Conversion complete flag or conversion complete interrupt • Selectable ADC clock 5.4 Functional Description The ADC provides eight pins for sampling external sources at pins PTB7/AD7–PTB0/AD0.
INTERNAL DATA BUS READ DDRB/DDRB WRITE DDRB/DDRD DDRBx RESET WRITE PTB DISABLE PTB/Dx PTBx ADC CHANNEL x READ PTB DISABLE ADC DATA REGISTER CONVERSION INTERRUPT COMPLETE LOGIC AIEN ADC BUS CLOCK ADCH4–ADCH0 ADC CLOCK COCO CGMXCLK ADC VOLTAGE IN (ADVIN) CHANNEL SELECT CLOCK GENERATOR ADIV2–ADIV0 ADICLK Figure 5-1. ADC Block Diagram 5.4.1 ADC Port I/O Pins PTB7/AD7–PTB0/AD0 are general-purpose I/O (input/output) pins that share with the ADC channels.
5.4.2 Voltage Conversion When the input voltage to the ADC equals VREFH, the ADC converts the signal to $FF (full scale). If the input voltage equals VSSAD, the ADC converts it to $00. Input voltages between VREFH and VSSAD are a straight-line linear conversion. All other input voltages will result in $FF, if greater than VREFH. NOTE: Input voltage should not exceed the analog supply voltages. 5.4.3 Conversion Time Conversion starts after a write to the ADSCR.
5.5 Interrupts When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC conversion. A CPU interrupt is generated if the COCO/IDMAS bit is at logic 0. If COCO/IDMAS bit is set, a DMA interrupt is generated. The COCO/IDMAS bit is not used as a conversion complete flag when interrupts are enabled. 5.6 Low-Power Modes The WAIT and STOP instruction can put the MCU in low powerconsumption standby modes. 5.6.1 Wait Mode The ADC continues normal operation during wait mode.
5.7.1 ADC Analog Power Pin (VDDAD)/ADC Voltage Reference High Pin (VREFH) The ADC analog portion uses VDDAD as its power pin. Connect the VDDAD pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDAD for good results. NOTE: For maximum noise immunity, route VDDAD carefully and place bypass capacitors as close as possible to the package. 5.7.2 ADC Analog Ground Pin (VSSAD)/ADC Voltage Reference Low Pin (VREFL) The ADC analog portion uses VSSAD as its ground pin.
5.8.1 ADC Status and Control Register Function of the ADC status and control register (ADSCR) is described here. Address: $0003C Bit 7 6 5 4 3 2 1 Bit 0 Write: COCO/ IDMAS AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Reset: 0 0 0 1 1 1 1 1 Read: Figure 5-2.
AIEN — ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled ADCO — ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion.
Table 5-1.
5.8.3 ADC Clock Register The ADC clock register (ADCLK) selects the clock frequency for the ADC. Address: Read: Write: Reset: $0003E Bit 7 6 5 4 ADIV2 ADIV1 ADIV0 ADICLK 0 0 0 0 3 2 1 Bit 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 5-4. ADC Clock Register (ADCLK) ADIV2–ADIV0 — ADC Clock Prescaler Bits ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 5-2 shows the available clock configurations.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be guaranteed. 1 = Internal bus clock 0 = External clock (CGMXCLK) ADC input clock frequency ----------------------------------------------------------------------- = 1MHz ADIV2 –ADIV0 MC68HC908GP20 — Rev 2.
Advance Information 98 MC68HC908GP20 — Rev 2.
Advance Information — MC68HC908GP20 Section 6. Break Module (BRK) 6.1 Contents 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 6.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . 102 6.4.2 CPU During Break Interrupts. . . . . . . . . . . . . .
6.3 Features Features of the break module include: • Accessible input/output (I/O) registers during the break interrupt • CPU-generated break interrupts • Software-generated break interrupts • COP disabling during break interrupts 6.4 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to the CPU.
IAB15–IAB8 BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB15–IAB0 CONTROL BREAK 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB7–IAB0 Figure 6-1. Break Module Block Diagram Addr.
6.4.1 Flag Protection During Break Interrupts The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. 6.4.2 CPU During Break Interrupts The CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) The break interrupt begins after completion of the CPU instruction in progress.
6.5.2 Stop Mode A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. 6.6 Break Module Registers These registers control and monitor operation of the break module: • Break status and control register (BRKSCR) • Break address register high (BRKH) • Break address register low (BRKL) • SIM break status register (SBSR) • SIM break flag control register (SBFCR) 6.6.
BRKA — Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine. Reset clears the BRKA bit. 1 = (When read) Break address match 0 = (When read) No break address match 6.6.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address.
6.6.3 Break Status Register The break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode. The flag is useful in applications requiring a return to wait mode after exiting from a break interrupt. Address: $FE00 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 1 0 0 BW 0 Write: R R R R R R NOTE R Reset: 0 0 0 1 0 0 0 0 R = Reserved Note: Writing a logic 0 clears BW. Figure 6-6.
6.6.4 Break Flag Control Register The break flag control register (SBFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. Address: Read: Write: Reset: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 R = Reserved Figure 6-7. SIM Break Flag Control Register (SBFCR) BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state.
Advance Information — MC68HC908GP20 Section 7. Clock Generator Module (CGMC) 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 7.4.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7.4.2 Phase-Locked Loop Circuit (PLL) .
7.6.5 7.6.6 7.7 PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . . 131 PLL Reference Divider Select Register. . . . . . . . . . . . . . . 132 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 7.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .
7.
OSCILLATOR (OSC) OSC2 CGMXCLK (TO: SIM, TIMTB15A, ADC) OSC1 SIMOSCEN (FROM SIM) OSCSTOPENB (FROM CONFIG) PHASE-LOCKED LOOP (PLL) CGMRDV REFERENCE DIVIDER CGMRCLK CLOCK SELECT CIRCUIT BCS RDS3–RDS0 VDDA CGMXFC ÷2 A CGMOUT B S* (TO SIM) *WHEN S = 1, CGMOUT = B VSSA SIMDIV2 (FROM SIM) VPR1–VPR0 VRS7–VRS0 PHASE DETECTOR VOLTAGE CONTROLLED OSCILLATOR LOOP FILTER CGMVCLK PLL ANALOG LOCK DETECTOR LOCK CGMVDV AUTOMATIC MODE CONTROL AUTO ACQ INTERRUPT CONTROL PLLIE MUL11–MUL0 PRE1–PRE
7.4.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration module (SIM) or the OSCSTOPENB bit in the CONFIG register enable the crystal oscillator circuit. The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency.
The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGM/XFC noise. The VCO frequency is bound to a range from roughly one-half to twice the center-of-range frequency, fVRS. Modulating the voltage on the CGM/XFC pin changes the frequency within this range. By design, fVRS is equal to the nominal center-of-range frequency, fNOM, (38.4 kHz) times a linear factor, L, and a power-of-two factor, E, or (L × 2E)fNOM.
frequency, fRDV. The circuit determines the mode of the PLL and the lock condition based on this comparison. 7.4.4 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: • Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency.
to use as the source for the base clock. (See 7.4.8 Base Clock Selector Circuit.) If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. (See 7.7 Interrupts for information and precautions on using interrupts.) The following conditions apply when the PLL is in automatic bandwidth control mode: • The ACQ bit (See 7.6.2 PLL Bandwidth Control Register.
The following conditions apply when in manual mode: • ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear. • Before entering tracking mode (ACQ = 1), software must wait a given time, tACQ (See 7.9 Acquisition/Lock Time Specifications.), after turning on the PLL by setting PLLON in the PLL control register (PCTL).
P, the power of two multiplier, and N, the range multiplier, are integers. In cases where desired bus frequency has some tolerance, choose fRCLK to a value determined either by other module requirements (such as modules which are clocked by CGMXCLK), cost requirements, or ideally, as high as the specified range allows. See Section 23. Preliminary Electrical Specifications. Choose the reference divider, R = 1. After choosing N and P, the actual bus frequency can be determined using equation in 2 above.
Then recalculate N: R × f VCLKDES N = round ------------------------------------- P f ×2 RCLK MC68HC908GP20 — Rev 2.
6. Calculate and verify the adequacy of the VCO and bus frequencies fVCLK and fBUS. P f VCLK = ( 2 × N ⁄ R ) × f RCLK f BUS = ( f VCLK ) ⁄ 4 7. Select the VCO’s power-of-two range multiplier E, according to this table: Frequency Range E 0 < fVCLK < 9,830,400 0 9,830,400 ≤ fVCLK < 19,660,800 1 19,660,800 ≤ fVCLK < 39,321,600 2 NOTE: Do not program E to a value of 3. 8. Select a VCO linear range multiplier, L, where fNOM = 38.
11. Program the PLL registers accordingly: a. In the PRE bits of the PLL control register (PCTL), program the binary equivalent of P. b. In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E. c. In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high (PMSH), program the binary equivalent of N. d. In the PLL VCO range select register (PMRS), program the binary coded equivalent of L. e.
7.4.7 Special Programming Exceptions The programming method described in 7.4.6 Programming the PLL does not account for three possible exceptions. A value of 0 for R, N, or L is meaningless when used in the equations given. To account for these exceptions: • A 0 value for R or N is interpreted exactly the same as a value of 1. • A 0 value for L disables the PLL and prevents its selection as the source for the base clock. (See 7.4.8 Base Clock Selector Circuit.) 7.4.
7.4.9 CGMC External Connections In its typical configuration, the CGMC requires up to nine external components. Five of these are for the crystal oscillator and two or four are for the PLL. The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 7-2. Figure 7-2 shows only the logical representation of the internal components and may not represent actual circuitry.
SIMOSCEN OSCSTOPENB (FROM CONFIG) CGMXCLK OSC1 CGMXFC OSC2 VSSA VDDA VDD RB 10 k RS CBYP 0.1 µF 0.01 µF 0.47 µF X1 C1 C2 Note: Filter network in box can be replaced with a 0.47 µF capacitor, but will degrade stability. Figure 7-2. CGMC External Connections 7.5 I/O Signals The following paragraphs describe the CGMC I/O signals. 7.5.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 7.5.
7.5.3 External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is connected to this pin. (See Figure 7-2.) NOTE: To prevent noise problems, the filter network should be placed as close to the CGMXFC pin as possible, with minimum routing distances and no routing of other signals across the network. 7.5.4 PLL Analog Power Pin (VDDA) VDDA is a power pin used by the analog portions of the PLL.
7.5.8 Crystal Output Frequency Signal (CGMXCLK) CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes directly from the crystal oscillator circuit. Figure 7-2 shows only the logical relation of CGMXCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be unstable at startup. 7.5.
• PLL VCO range select register (PMRS) (See 7.6.5 PLL VCO Range Select Register.) • PLL reference divider select register (PMDS) (See 7.6.6 PLL Reference Divider Select Register.) Figure 7-3 is a summary of the CGMC registers. Addr.
7.6.1 PLL Control Register The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits. Address: $0036 Bit 7 Read: Write: Reset: PLLIE 0 6 PLLF 0 5 4 3 2 1 Bit 0 PLLON BCS PRE1 PRE0 VPR1 VPR0 1 0 0 0 0 0 = Unimplemented Figure 7-4.
PLLON — PLL On Bit This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See 7.4.8 Base Clock Selector Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up. 1 = PLL on 0 = PLL off BCS — Base Clock Select Bit This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGMC output, CGMOUT.
Table 7-2. PRE 1 and PRE0 Programming PRE1 and PRE0 P Prescaler Multiplier 00 0 1 01 1 2 10 2 4 11 3 8 VPR1 and 0 — VCO Power-of-Two Range Select Bits These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction with L (See 7.4.3 PLL Circuits, 7.4.6 Programming the PLL, and 7.6.5 PLL VCO Range Select Register.) controls the hardware center-of-range frequency, fVRS. VPR1:VPR0 cannot be written when the PLLON bit is set. Reset clears these bits.
Bit 7 Read: Write: Reset: AUTO 0 6 4 3 2 1 0 0 0 0 0 0 0 0 0 = Unimplemented R LOCK 0 5 ACQ Bit 0 R 0 = Reserved Figure 7-5. PLL Bandwidth Control Register (PBWC) AUTO — Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit.
7.6.3 PLL Multiplier Select Register High The PLL multiplier select register high (PMSH) contains the programming information for the high byte of the modulo feedback divider. Address: Read: $0038 Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 MUL11 MUL10 MUL9 MUL8 0 0 0 0 = Unimplemented Figure 7-6.
7.6.4 PLL Multiplier Select Register Low The PLL multiplier select register low (PMSL) contains the programming information for the low byte of the modulo feedback divider. Address: Read: Write: Reset: $0038 Bit 7 6 5 4 3 2 1 Bit 0 MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0 0 1 0 0 0 0 0 0 Figure 7-7.
7.6.5 PLL VCO Range Select Register NOTE: PMRS may be called PVRS on other HC08 derivatives. The PLL VCO range select register (PMRS) contains the programming information required for the hardware configuration of the VCO. Address: Read: Write: Reset: $003A Bit 7 6 5 4 3 2 1 Bit 0 VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0 0 1 0 0 0 0 0 0 Figure 7-8.
7.6.6 PLL Reference Divider Select Register NOTE: PMDS may be called PRDS on other HC08 derivatives. The PLL reference divider select register (PMDS) contains the programming information for the modulo reference divider. Address: Read: $003B Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 RDS3 RDS2 RDS1 RDS0 0 0 0 1 = Unimplemented Figure 7-9.
7.7 Interrupts When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and PLLF reads as logic 0.
mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost. 7.8.2 Stop Mode If the OSCSTOPENB bit in the CONFIG register is cleared (default), then the STOP instruction disables the CGMC (oscillator and phase locked loop) and holds low all CGMC outputs (CGMXCLK, CGMOUT, and CGMINT).
7.9 Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. 7.9.1 Acquisition/Lock Time Definitions Typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input.
7.9.2 Parametric Influences on Reaction Time Acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time. The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRDV. This frequency is the input to the phase detector and controls how often the PLL makes corrections.
filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. 7.9.3 Choosing a Filter As described in 7.9.2 Parametric Influences on Reaction Time, the external filter network is critical to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply voltage. Either of the filter networks in Figure 7-10 is recommended when using a 32.768-kHz reference crystal.
Advance Information — MC68HC908GP20 Section 8. Configuration Register (CONFIG) 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 8.2 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2.
NOTE: On a FLASH device, the options except LVI5OR3 are one-time writeable by the user after each reset. The LVI5OR3 bit is one-time writeable by the user only after each POR (power-on reset). The CONFIG registers are not in the FLASH memory but are special registers containing onetime writeable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 8-1 and Figure 8-2.
NOTE: For VDD > 3.6 V: The voltage regular must always be enabled. The charge pump must have the voltage regulator on to provide the proper voltage to the FLASH memory. For VDD < 3.6 V: The voltage regulator may be disabled to conserve power. The charge pump does not use the voltage regulator when VDD is less than 3.6 V, so the voltage regulator can be turned off. Leaving the voltage regulator enabled will not cuase any harm. The chip will merely consume more power than necessary.
LVISTOP — LVI Enable in Stop Mode Bit When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode. Reset clears LVISTOP. (See 3.6.2 Stop Mode.) 1 = LVI enabled during stop mode 0 = LVI disabled during stop mode LVIRSTD — LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module. (See Section 14. Low-Voltage Inhibit (LVI).) 1 = LVI module resets disabled 0 = LVI module resets enabled LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module.
NOTE: When the LVISTOP is enabled, the system stabilization time for power on reset and long stop recovery (both 4096 CGMXCLK cycles) gives a delay longer than the enable time for the LVI. There is no period where the MCU is not protected from a low power condition. However, when using the short stop recovery configuration option, the 32-CGMXCLK delay is less than the LVI’s turn-on time and there exists a period in startup where the LVI is not protecting the MCU.
Advance Information 144 MC68HC908GP20 — Rev 2.
Advance Information — MC68HC908GP20 Section 9. Computer Operating Properly (COP) 9.1 Contents 9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 9.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 9.4.1 CGMXCLK. . . . . .
9.2 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG register. 9.3 Functional Description Figure 9-1 shows the structure of the COP module.
The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 218 – 24 or 213 – 24 CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS, in the configuration register. With a 213 – 24 CGMXCLK cycle overflow option, a 32.768-kHz crystal gives a COP timeout period of 250 ms.
9.4.3 COPCTL Write Writing any value to the COP control register (COPCTL) (see 9.5 COP Control Register) clears the COP counter and clears bits 12 through 5 of the prescaler. Reading the COP control register returns the low byte of the reset vector. 9.4.4 Power-On Reset The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up. 9.4.5 Internal Reset An internal reset clears the COP prescaler and the COP counter. 9.4.
9.5 COP Control Register The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector. Address: $FFFF Bit 7 6 5 4 3 Read: Low byte of reset vector Write: Clear COP counter Reset: Unaffected by reset 2 1 Bit 0 Figure 9-2. COP Control Register (COPCTL) 9.6 Interrupts The COP does not generate CPU interrupt requests. 9.
9.8.1 Wait Mode The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. 9.8.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode.
Advance Information — MC68HC908GP20 Section 10. Central Processor Unit (CPU) 10.1 Contents 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 10.4.2 Index Register . . .
10.
7 0 ACCUMULATOR (A) 15 0 H X INDEX REGISTER (H:X) 0 15 STACK POINTER (SP) 0 15 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 10-1. CPU Registers 10.4.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
10.4.2 Index Register The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Read: Write: Reset: Figure 10-4. Stack Pointer (SP) NOTE: The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations. 10.4.
10.4.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 10-6.
I — Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled NOTE: To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically.
C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7 10.5 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set.
10.6.2 Stop Mode The STOP instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay. 10.
10.
V H I N Z C Mn ← 0 Cycles Description Operand Operation Effect on CCR Opcode Source Form Address Mode Table 10-1.
V H I N Z C Cycles Description Operand Operation Effect on CCR Opcode Source Form Address Mode Table 10-1.
V H I N Z C CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP Compare A with M COM opr COMA COMX COM opr,X COM ,X COM opr,SP Complement (One’s Complement) CPHX #opr CPHX opr Compare H:X with M CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M DAA Decimal Adjust A DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP Decrement DIV Di
V H I N Z C INC opr INCA INCX INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Increment Jump to Subroutine Load A from M LDHX #opr LDHX opr Load H:X from M LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP Logical Shift Right MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr Move MUL Unsigned multiply 164 4 1 1 4 3 5 PC ← Jump Address dd hh ll ee ff ff 2 3 4 3 2 PC ← (PC) + n (n = 1, 2,
V H I N Z C DIR INH – – ↕ ↕ ↕ INH IX1 IX SP1 30 dd 40 50 60 ff 70 9E60 ff Cycles Description Operand Operation Effect on CCR Opcode Source Form Address Mode Table 10-1.
V H I N Z C IMM DIR EXT IX2 – – ↕ ↕ ↕ IX1 IX SP1 SP2 A2 B2 C2 D2 E2 F2 9EE2 9ED2 ii dd hh ll ee ff ff Cycles Description Operand Operation Effect on CCR Opcode Source Form Address Mode Table 10-1.
V H I N Z C TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP Test for Negative or Zero TSX Transfer SP to H:X TXA Transfer X to A TXS Transfer H:X to SP A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N (A) – $00 or (X) – $00 or (M) – $00 0 – – ↕ ↕ DIR INH – INH IX1 IX SP1 3D dd 4D 5D 6D ff 7D 9E6D ff Cycles Description Operand Operation Effect on CCR Opcode Source Form Address Mode Table 10-1.
Advance Information 168 Table 10-2. Opcode Map Bit Manipulation DIR DIR MSB Branch REL DIR INH 3 4 0 2 3 4 5 6 7 8 9 A B C MC68HC908GP20 — Rev 2.
Advance Information — MC68HC908GP20 Section 11. FLASH Memory 11.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 11.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.5 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 11.5.1 FLASH Charge Pump Frequency Control . . . . . .
in the FLASH array is organized into pages within rows. There are eight pages of memory per row with eight bytes per page. The minimum erase block size is a single row, 64 bytes. Programming is performed on a per page basis; eight bytes at a time. The address ranges for the user memory and vectors are: • $B000–$FDFF; user memory • $FF80; block protect register • $FE08; FLASH control register • $FFDC–$FFFF; These locations are reserved for user-defined interrupt and reset vectors.
NOTE: A security feature prevents viewing of the FLASH contents.1 11.4 FLASH Control Register The FLASH control register (FLCR) controls FLASH program, erase, and margin read operations. Address: Read: Write: Reset: $FE08 Bit 7 6 5 4 3 2 1 Bit 0 FDIV1 FDIV0 BLK1 BLK0 HVEN MARGIN ERASE PGM 0 0 0 0 0 0 0 0 Figure 11-1.
HVEN — High-Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program/margin read or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MARGIN — Margin Read Control Bit This read/write bit configures the memory for margin read operation.
11.5 Charge Pump The internal FLASH charge pump is an analog circuit that provides the proper voltage to the FLASH memory when reading, programming, and erasing the memory arrays. 11.5.1 FLASH Charge Pump Frequency Control The internal charge pump required for program, margin read, and erase operations is designed to operate most efficiently with a 2 MHz clock. The charge pump clock is derived from the bus clock.
11.6 FLASH Erase Operation Use this step-by-step procedure to erase a block of FLASH memory to read as logic 0: 1. If operating voltage is below 3.6 V, set the PMPSGVLVEN bit in the CONFIG2 register. (See 8.3 Functional Description.) 2. Set the ERASE bit, the BLK0, BLK1, FDIV0, and FDIV1 bits in the FLASH control register. See Table 11-1 for FDIV settings. See Table 11-2 for block sizes. 3. To ensure target portion of array is unprotected, read the FLASH block protect register. (See 11.
Table 11-2.
$FFDC to $FFFF. This block erase can also be accomplished by writing to any FLASH address in which A14 = 1 while BLK1 = 0 and BLK0 = 1. In the 1/5 array case (A14 = 0, BLK1 = 0, BLK0 = 1) the state of A14 = 0 determines that the range from $B000 to $BFFF is erased. For example, writing to address $B123 (A14 = 0, BLK1 = 0, BLK0 = 1) will erase the range $B000 to $BFFF. This block erase can also be accomplished by writing to any FLASH address in which A14 = 0 while BLK1 = 0 and BLK0 = 1.
In the other “single row case” (A6 = 0, BLK1 = 1, BLK0 = 1), the state of A6 = 0 determines that the range from $<0000> to $<1111> is erased. Address bits A15–A7 indicate arbitrary address bit values defined in the desired erase address range while the remaining lower bits A6–A0 are fixed as shown.
the location will be read as $FF (1111 1111 binary). (0s cannot be programmed. 0s only result from the erase operation.) To program and margin read the FLASH memory, use this procedure: 1. If operating voltage is below 3.6 V, set the PMPSGVLVEN bit in the CONFIG2 register. (See 8.3 Functional Description.) 2. Set the PGM, FDIV1, and FDIV0 bits in the FLASH control register. This configures the memory for program operation and enables the latching of address and data for programming. 3.
Smart Programming Algorithm PROGRAM FLASH Page Program/Margin Read Procedure Note: This algorithm is mandatory for programming the FLASH. INITIALIZE ATTEMPT COUNTER TO 0 Note: This page program algorithm assumes the page/s to be programmed are initially erased.
11.8 FLASH Block Protection NOTE: In performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit. Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting blocks of memory from unintentional erase or program operations due to system malfunction.
11.9 FLASH Block Protect Register The block protect register (FLBPR) is implemented as a byte within the FLASH memory. Each bit, when programmed, protects a range of addresses in the FLASH. Address: Read: Write: Reset: $FF80 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 BPR3 BPR2 BPR1 BPR0 U U U U U U U U U = Unaffected by reset. Initial value from factory is 0. Figure 11-3.
BPR0 — Block Protect Register Bit 0 In a larger memory, this bit would protect the memory contents in the address range $8000 to $FFFF. It is redundant in this implementation. Setting this bit locks everything from $B000 to $FFFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program Bit 7, Bit 6, Bit 5, and Bit 4 These bits do not affect FLASH block protection. They are extra bits that can be used by the user as readable/writeable bits.
11.11 Stop Mode When the MCU is put into stop mode, if the FLASH is in read mode, it will be put into low-power standby. Exit from stop is possible with an external interrupt, such as IRQ, keyboard interrupt, or reset. The STOP instruction should not be executed while performing a program or erase operation on the FLASH. When the MCU is put into stop mode, the charge pump for the FLASH is disabled so that either a program or erase operation will not continue.
Advance Information 184 MC68HC908GP20 — Rev 2.
Advance Information — MC68HC908GP20 Section 12. External Interrupt (IRQ) 12.1 Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 12.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.
12.4 Functional Description A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Figure 12-1 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of the following actions occurs: • Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears the latch that caused the vector fetch.
NOTE: The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. INTERNAL ADDRESS BUS ACK RESET TO CPU FOR BIL/BIH INSTRUCTIONS VECTOR FETCH DECODER VDD INTERNAL PULLUP DEVICE VDD IRQF D IRQ CLR Q SYNCHRONIZER CK IRQ INTERRUPT REQUEST IRQ FF IMASK MODE TO MODE SELECT LOGIC HIGH VOLTAGE DETECT Figure 12-1. IRQ Module Block Diagram Addr.
12.5 IRQ Pin A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and lowlevel-sensitive. With MODE set, both of the following actions must occur to clear IRQ: • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch.
NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. 12.6 IRQ Module During Break Interrupts The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the latch during the break state. See Section 6. Break Module (BRK). To allow software to clear the IRQ latch during a break interrupt, write a logic 1 to the BCFE bit.
Address: $001D Bit 7 6 5 4 Read: 3 2 IRQF 0 Write: Reset: ACK 0 0 0 0 0 0 1 Bit 0 IMASK MODE 0 0 = Unimplemented Figure 12-3. IRQ Status and Control Register (INTSCR) IRQF — IRQ Flag Bit This read-only status bit is high when the IRQ interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending ACK — IRQ Interrupt Request Acknowledge Bit Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always reads as logic 0. Reset clears ACK.
Advance Information — MC68HC908GP20 Section 13. Keyboard Interrupt Module (KBI) 13.1 Contents 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 13.5 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 13.6 Low-Power Modes .
13.3 Features • Eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask • Hysteresis buffers • Programmable edge-only or edge- and level- interrupt sensitivity • Exit from low-power modes • I/O (input/output) port bit(s) software configurable with pullup device(s) if configured as input port bit(s) 13.
MC68HC908GP20 — Rev 2.1 Freescale Semiconductor INTERNAL BUS KBD0 VECTOR FETCH DECODER ACKK VDD KEYF RESET . TO PULLUP ENABLE D CLR Q SYNCHRONIZER . CK KB0IE . KEYBOARD INTERRUPT FF KBD7 KEYBOARD INTERRUPT REQUEST IMASKK MODEK TO PULLUP ENABLE KB7IE Figure 13-1. Keyboard Module Block Diagram Addr.
If the MODEK bit is set, the keyboard interrupt pins are both falling edgeand low-level sensitive, and both of the following actions must occur to clear a keyboard interrupt request: • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register (INTKBSCR).
NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin. 13.5 Keyboard Initialization When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. Therefore, a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1.
13.6.1 Wait Mode The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. 13.6.2 Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. 13.
13.8 I/O Registers These registers control and monitor operation of the keyboard module: • Keyboard status and control register (INTKBSCR) • Keyboard interrupt enable register (INTKBIER) 13.8.
ACKK — Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as logic 0. Reset clears ACKK. IMASKK — Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit.
Advance Information — MC68HC908GP20 Section 14. Low-Voltage Inhibit (LVI) 14.1 Contents 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 14.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 14.4.2 Forced Reset Operation . . . .
14.4 Functional Description Figure 14-1 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator. Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor VDD voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI module to generate a reset when VDD falls below a voltage, VTRIPF. Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode.
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices. VDD STOP INSTRUCTION LVISTOP FROM CONFIG FROM CONFIG LVIRSTD LVIPWRD FROM CONFIG LOW VDD DETECTOR VDD > LVITrip = 0 LVI RESET VDD ≤ LVITrip = 1 LVIOUT LVI5OR3 FROM CONFIG Figure 14-1. LVI Module Block Diagram Addr.
14.4.2 Forced Reset Operation In applications that require VDD to remain above the VTRIPF level, enabling LVI resets allows the LVI module to reset the MCU when VDD falls below the VTRIPF level. In the configuration register, the LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets. 14.4.
14.5 LVI Status Register The LVI status register (LVISR) indicates if the VDD voltage was detected below the VTRIPF level. Address: $FE0C Bit 7 Read: LVIOUT 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: 0 = Unimplemented Figure 14-3. LVI Status Register (LVISR) LVIOUT — LVI Output Bit This read-only flag becomes set when the VDD voltage falls below the VTRIPF trip voltage. (See Table 14-1.) Reset clears the LVIOUT bit. Table 14-1.
14.6 LVI Interrupts The LVI module does not generate interrupt requests. 14.7 Low-Power Modes The STOP and WAIT instructions put the MCU in low powerconsumption standby modes. 14.7.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 14.7.2 Stop Mode If enabled in stop mode (LVISTOP set), the LVI module remains active in stop mode.
Advance Information — MC68HC908GP20 Section 15. Monitor ROM (MON) 15.1 Contents 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 15.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 15.4.2 Data Format . . . . . . . . . . . . . . .
15.3 Features Features of the monitor ROM include: • Normal user-mode pin functionality • One pin dedicated to serial communication between monitor ROM and host computer • Standard mark/space non-return-to-zero (NRZ) communication with host computer • Execution of code in RAM or FLASH • FLASH memory security feature1 • FLASH memory programming interface • Enhanced PLL (phase-locked loop) option to allow use of external 32.768-kHz crystal to generate internal frequency of 2.
68HC08 RST 0.1 µF VTST (SEE NOTE 3) RESET VECTORS $FFFE 10 kΩ (SEE NOTES 2 SW2 AND 3) C C D VDDA $FFFF IRQ VDDA CGMXFC 0.01 µF 10 k 0.47 µF SW3 (SEE NOTE 2) C 10 µF + MC145407 3 20 + D 10 MΩ 1 6–30 pF 10 µF 18 C 32.768 kHz XTAL 4 10 µF 17 330 kΩ + + 2 19 DB-25 2 5 16 3 6 15 10 µF VDD SW4 (SEE NOTE 2) OSC1 OSC2 PTA7 VSS VSSAD/VREFL D VSSA 6–30 pF VDD VDD VDDAD/VREFH 0.
between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor. The monitor code has been updated from previous versions of the monitor code to allow enabling the PLL to generate the internal clock, provided the reset vector is blank, when the device is being clocked by a low-frequency crystal.
MC68HC908GP20 — Rev 2.1 Freescale Semiconductor Table 15-1. Monitor Mode Signal Requirements and Options IRQ RESET $FFFE/ $FFFF PLL PTC0 PTC1 PTC3 External Clock(1) CGMOUT Bus Frequency For Serial Communication COP Comment Baud PTA0 PTA7 Rate(2) (3) X GND X X X X X X 0 0 Disabled X X 0 No operation until reset goes high VTST VDD or VTST X OFF 1 0 0 4.9152 MHz 4.9152 MHz 2.
PTC3 pin low when entering monitor mode causes a bypass of a divideby-two stage at the oscillator only if VTST is applied to IRQ. In this event, the CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency.
POR RESET IS VECTOR BLANK? NO NORMAL USER MODE YES MONITOR MODE EXECUTE MONITOR CODE POR TRIGGERED? NO YES Figure 15-2. Low-Voltage Monitor Mode Entry Flowchart Enter monitor mode with pin configuration shown in Figure 15-1 by pulling RST low and then high. The rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can change. Once out of reset, the MCU waits for the host to send eight security bytes. (See 15.5 Security.
Table 15-2 summarizes the differences between user mode and monitor mode. Table 15-2. Mode Differences Functions Modes Reset Vector High Reset Vector Low Break Vector High Break Vector Low SWI Vector High SWI Vector Low User $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD Monitor $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD 15.4.2 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical.
15.4.4 Baud Rate The communication baud rate is controlled by the crystal frequency and the state of the PTC3 pin (when IRQ is set to VTST) upon entry into monitor mode. When PTC3 is high, the divide by ratio is 1024. If the PTC3 pin is at logic 0 upon entry into monitor mode, the divide by ratio is 512. If monitor mode was entered with VDD on IRQ, then the divide by ratio is set at 1024, regardless of PTC3.
• READSP (read stack pointer) • RUN (run user program) The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command. A delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned. The data returned by a read command appears after the echo of the last byte of the command.
A brief description of each monitor mode command is given in Table 15-4 through Table 15-9. Table 15-4. READ (Read Memory) Command Description Read byte from memory Operand 2-byte address in high-byte:low-byte order Data Returned Returns contents of specified address Opcode $4A Command Sequence SENT TO MONITOR ADDRESS HIGH READ READ ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA ECHO RETURN Table 15-5.
Table 15-6. IREAD (Indexed Read) Command Description Read next 2 bytes in memory from last address accessed Operand 2-byte address in high byte:low byte order Data Returned Returns contents of next two addresses Opcode $1A Command Sequence FROM HOST IREAD IREAD DATA ECHO DATA RETURN Table 15-7.
A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. Table 15-8. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Data Returned Returns incremented stack pointer value (SP + 1) in high-byte:lowbyte order Opcode $0C Command Sequence FROM HOST READSP SP HIGH READSP ECHO SP LOW RETURN Table 15-9.
The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can modify the stacked CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at addresses SP + 5 and SP + 6.
VDD 4096 + 32 CGMXCLK CYCLES RST 24 BUS CYCLES COMMAND PA7 BYTE 8 BYTE 2 BYTE 1 256 BUS CYCLES (MINIMUM) FROM HOST PA0 4 BREAK 2 NOTES: 1 = Echo delay, 2 bit times 2 = Data return delay, 2 bit times 4 = Wait 1 bit time before sending next byte. 1 COMMAND ECHO 1 BYTE 8 ECHO BYTE 1 ECHO FROM MCU 1 BYTE 2 ECHO 4 1 Figure 15-8.
If the security sequence fails, the device can be reset and brought up in monitor mode to attempt another entry. After failing the security sequence, the FLASH mode can also be bulk erased by executing an erase routine that was downloaded into internal RAM. The bulk erase operation clears the security code locations so that all eight security bytes become $00. Advance Information 220 MC68HC908GP20 — Rev 2.
Advance Information — MC68HC908GP20 Section 16. Input/Output (I/O) Ports 16.1 Contents 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 16.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 16.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 16.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . 226 16.3.3 Port A Input Pullup Enable Register .
16.2 Introduction Thirty-three (33) bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable as inputs or outputs. All individual bits within port A, port C, and port D are software configurable with pullup devices if configured as input port bits. The pullup devices are automatically and dynamically disabled when a port bit is switched to output mode. NOTE: Addr. Connect any unused I/O pins to an appropriate logic level, either VDD or VSS.
Addr.
Table 16-1.
16.3 Port A Port A is an 8-bit special-function port that shares all eight of its pins with the keyboard interrupt (KBI) module. Port A also has software configurable pullup devices if configured as an input port. 16.3.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the eight port A pins.
16.3.2 Data Direction Register A Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer. Address: Read: Write: Reset: $0004 Bit 7 6 5 4 3 2 1 Bit 0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 0 0 0 0 Figure 16-3.
READ DDRA ($0004) INTERNAL DATA BUS WRITE DDRA ($0004) DDRAx RESET WRITE PTA ($0000) PTAx PTAx VDD PTAPUEx READ PTA ($0000) INTERNAL PULLUP DEVICE Figure 16-4. Port A I/O Circuit When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 16-2 summarizes the operation of the port A pins. Table 16-2.
16.3.3 Port A Input Pullup Enable Register The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each of the eight port A pins. Each bit is individually configurable and requires that the data direction register, DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRA is configured for output mode.
16.4 Port B Port B is an 8-bit special-function port that shares all eight of its pins with the analog-to-digital converter (ADC) module. 16.4.1 Port B Data Register The port B data register (PTB) contains a data latch for each of the eight port pins. Address: Read: Write: $0001 Bit 7 6 5 4 3 2 1 Bit 0 PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 AD2 AD1 AD0 Reset: Alternate Function: Unaffected by reset AD7 AD6 AD5 AD4 AD3 Figure 16-6.
16.4.2 Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer. Address: Read: Write: Reset: $0005 Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 Figure 16-7.
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 16-3 summarizes the operation of the port B pins. Table 16-3.
16.5 Port C Port C is a 7-bit, general-purpose bidirectional I/O port. Port C also has software configurable pullup devices if configured as an input port. 16.5.1 Port C Data Register The port C data register (PTC) contains a data latch for each of the seven port C pins. Address: $0002 Bit 7 Read: Write: 0 6 5 4 3 2 1 Bit 0 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 Reset: Unaffected by reset = Unimplemented Figure 16-9.
16.5.2 Data Direction Register C Data direction register C (DDRC) determines whether each port C pin is an input or an output. Writing a logic 1 to a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer. Address: $0006 Bit 7 Read: 0 Write: Reset: 0 6 5 4 3 2 1 Bit 0 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0 0 0 0 0 0 0 = Unimplemented Figure 16-10.
READ DDRC ($0006) INTERNAL DATA BUS WRITE DDRC ($0006) DDRCx RESET WRITE PTC ($0002) PTCx PTCx VDD PTCPUEx READ PTC ($0002) INTERNAL PULLUP DEVICE Figure 16-11. Port C I/O Circuit When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 16-4 summarizes the operation of the port C pins. Table 16-4.
16.5.3 Port C Input Pullup Enable Register The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each of the seven port C pins. Each bit is individually configurable and requires that the data direction register, DDRC, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRC is configured for output mode.
16.6 Port D Port D is an 8-bit special-function port that shares four of its pins with the serial peripheral interface (SPI) module and four of its pins with two timer interface (TIM1 and TIM2) modules. Port D also has software configurable pullup devices if configured as an input port. 16.6.1 Port D Data Register The port D data register (PTD) contains a data latch for each of the eight port D pins. NOTE: Bit 7 and bit 6 of PTD are not available in a 40-pin dual in-line package.
T1CH1 and T1CH0 — Timer 1 Channel I/O Bits The PTD7/T1CH1–PTD6/T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level select bits, ELSxB and ELSxA, determine whether the PTD7/T1CH1–PTD6/T1CH0 pins are timer channel I/O pins or general-purpose I/O pins. See Section 22. Timer Interface Module (TIM). SPSCK — SPI Serial Clock The PTD3/SPSCK pin is the serial clock input of the SPI module. When the SPE bit is clear, the PTD3/SPSCK pin is available for general-purpose I/O.
16.6.2 Data Direction Register D Data direction register D (DDRD) determines whether each port D pin is an input or an output. Writing a logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer. Address: Read: Write: Reset: $0007 Bit 7 6 5 4 3 2 1 Bit 0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 Figure 16-14.
READ DDRD ($0007) WRITE DDRD ($0007) DDRDx INTERNAL DATA BUS RESET WRITE PTD ($0003) PTDx PTDx VDD PTDPUEx READ PTD ($0003) INTERNAL PULLUP DEVICE Figure 16-15. Port D I/O Circuit When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 16-5 summarizes the operation of the port D pins. Table 16-5.
16.6.3 Port D Input Pullup Enable Register The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each of the eight port D pins. Each bit is individually configurable and requires that the data direction register, DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRD is configured for output mode.
16.7.1 Port E Data Register The port E data register contains a data latch for each of the two port E pins. Address: Read: $0008 Bit 7 6 5 4 3 2 0 0 0 0 0 0 Write: Reset: 1 Bit 0 PTE1 PTE0 RxD TxD Unaffected by reset Alternate Function: = Unimplemented Figure 16-17. Port E Data Register (PTE) PTE1 and PTE0 — Port E Data Bits PTE1 and PTE0 are read/write, software programmable bits.
16.7.2 Data Direction Register E Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer. Address: Read: $000C Bit 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: 1 Bit 0 DDRE1 DDRE0 0 0 = Unimplemented Figure 16-18.
INTERNAL DATA BUS READ DDRE ($000C) WRITE DDRE ($000C) RESET DDREx WRITE PTE ($0008) PTEx PTEx READ PTE ($0008) Figure 16-19. Port E I/O Circuit When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 16-6 summarizes the operation of the port E pins. Table 16-6.
Advance Information 244 MC68HC908GP20 — Rev 2.
Advance Information — MC68HC908GP20 Section 17. Random-Access Memory (RAM) 17.1 Contents 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 17.2 Introduction This section describes the 512 bytes of RAM (random-access memory). 17.3 Functional Description Addresses $0040 through $023F are RAM locations. The location of the stack RAM is programmable.
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE: Advance Information 246 Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. MC68HC908GP20 — Rev 2.
Advance Information — MC68HC908GP20 Section 18. Serial Communications Interface Module (SCI) 18.1 Contents 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 18.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 18.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 18.5.
18.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 18.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .269 18.9.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .272 18.9.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .275 18.9.4 SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 18.9.5 SCI Status Register 2 . . . . . . . . . . . . . . . . . .
MC68HC908GP20 — Rev 2.
18.4 Pin Name Conventions The generic names of the SCI I/O pins are: • RxD (receive data) • TxD (transmit data) SCI I/O (input/output) lines are implemented by sharing parallel I/O port pins. The full name of an SCI input or output reflects the name of the shared port pin. Table 18-1 shows the full names and the generic names of the SCI I/O pins. The generic pin names appear in the text of this section. Table 18-1.
INTERNAL BUS SCI DATA REGISTER ERROR INTERRUPT CONTROL RECEIVER INTERRUPT CONTROL DMA INTERRUPT CONTROL RECEIVE SHIFT REGISTER PTE1/RxD TRANSMITTER INTERRUPT CONTROL SCI DATA REGISTER TRANSMIT SHIFT REGISTER PTE0/TxD TXINV SCTIE R8 TCIE T8 SCRIE ILIE DMARE TE SCTE RE DMATE TC RWU SBK SCRF OR ORIE IDLE NF NEIE FE FEIE PE PEIE LOOPS LOOPS WAKEUP CONTROL SCIBDSRC FROM CONFIG FLAG CONTROL RECEIVE CONTROL ENSCI ENSCI TRANSMIT CONTROL BKF M RPF WAKE ILTY SL CGMXCLK A X B I
Addr.
18.5.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 18-3. 8-BIT DATA FORMAT BIT M IN SCC1 CLEAR START BIT START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 PARITY BIT BIT 6 BIT 7 9-BIT DATA FORMAT BIT M IN SCC1 SET BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 STOP BIT NEXT START BIT PARITY BIT BIT 6 BIT 7 BIT 8 STOP BIT NEXT START BIT Figure 18-3. SCI Data Formats 18.5.2 Transmitter Figure 18-4 shows the structure of the SCI transmitter.
SCIBDSRC FROM CONFIG2 SL A CGMXCLK X B IT12 SL = 0 => X = A SL = 1 => X = B INTERNAL BUS ÷ 16 SCI DATA REGISTER SCP1 11-BIT TRANSMIT SHIFT REGISTER STOP SCP0 SCR1 H SCR2 7 6 5 4 3 2 1 0 L PTE0/TxD MSB TXINV PTY PARITY GENERATION T8 DMATE DMATE SCTIE SCTE DMATE SCTE SCTIE TC TCIE BREAK ALL 0s PEN PREAMBLE ALL 1s M LOAD FROM SCDR TRANSMITTER DMA SERVICE REQUEST TRANSMITTER CPU INTERRUPT REQUEST SCR0 8 START BAUD DIVIDER SHIFT ENABLE PRESCALER ÷4 TRANSMITTER CONTROL LOGIC
18.5.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is the ninth bit (bit 8). 18.5.2.2 Character Transmission During an SCI transmission, the transmit shift register shifts a character out to the PTE0/TxD pin.
18.5.2.3 Break Characters Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register.
NOTE: When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current character shifts out to the TxD pin. Setting TE after the stop bit appears on TxD causes data previously written to the SCDR to be lost. Toggle the TE bit for a queued idle character when the SCTE bit becomes set and just before writing the next byte to the SCDR. 18.5.2.
18.5.3 Receiver Figure 18-5 shows the structure of the SCI receiver. 18.5.3.1 Character Length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7). 18.5.3.
INTERNAL BUS SCIBDSRC FROM CONFIG2 SCR1 SCP0 SCR0 PRESCALER BAUD DIVIDER ÷ 16 DATA RECOVERY PTE1/RxD CPU INTERRUPT REQUEST 8 7 6 5 M WAKE ILTY PEN PTY 4 3 2 1 0 L ALL 0s RPF ERROR CPU INTERRUPT REQUEST DMA SERVICE REQUEST H ALL 1s BKF 11-BIT RECEIVE SHIFT REGISTER STOP ÷4 SCI DATA REGISTER START SCR2 MSB SL CGMXCLK A X B IT12 SL = 0 => X = A SL = 1 => X = B SCP1 SCRF WAKEUP LOGIC PARITY CHECKING IDLE ILIE DMARE SCRF SCRIE DMARE SCRF SCRIE DMARE OR ORIE NF NEIE FE FEIE PE PEIE
18.5.3.3 Data Sampling The receiver samples the PTE1/RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate.
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 18-2 summarizes the results of the start bit verification samples. Table 18-2. Start Bit Verification RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag 000 Yes 0 001 Yes 1 010 Yes 1 011 No 0 100 Yes 1 101 No 0 110 No 0 111 No 0 Start bit verification is not successful if any two of the three verification samples are logic 1s.
NOTE: The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit. To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 18-4 summarizes the results of the stop bit samples. Table 18-4.
tolerance is much more than the degree of misalignment that is likely to occur. As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within the character. Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times. Slow Data Tolerance Figure 18-7 shows how much a slow received character can be misaligned without causing a noise error or a framing error.
With the misaligned character shown in Figure 18-7, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is 170 – 163 × 100 = 4.
For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 18-8, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times × 16 RT cycles = 176 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 170 – 176 × 100 = 3.53% -------------------------170 18.5.3.
SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. NOTE: With the WAKE bit clear, setting the RWU bit after the RxD pin has been idle may cause the receiver to wake up immediately. 18.5.3.
• Framing error (FE) — The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error CPU interrupt requests. • Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt requests. 18.
Refer to Section 3. Low-Power Modes for information on exiting stop mode. 18.7 SCI During Break Module Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit.
18.8.2 PTE1/RxD (Receive Data) The PTE1/RxD pin is the serial data input to the SCI receiver. The SCI shares the PTE1/RxD pin with port E. When the SCI is enabled, the PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in data direction register E (DDRE). 18.
Address: Read: Write: Reset: $0013 Bit 7 6 5 4 3 2 1 Bit 0 LOOPS ENSCI TXINV M WAKE ILTY PEN PTY 0 0 0 0 0 0 0 0 Figure 18-9. SCI Control Register 1 (SCC1) LOOPS — Loop Mode Select Bit This read/write bit enables loop mode operation. In loop mode the PTE1/RxD pin is disconnected from the SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use loop mode. Reset clears the LOOPS bit.
M — Mode (Character Length) Bit This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 18-5.) The ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears the M bit.
PTY — Parity Bit This read/write bit determines whether the SCI generates and checks for odd parity or even parity. (See Table 18-5.) Reset clears the PTY bit. 1 = Odd parity 0 = Even parity NOTE: Changing the PTY bit in the middle of a transmission or reception can generate a parity error. Table 18-5.
• Enables the transmitter • Enables the receiver • Enables SCI wakeup • Transmits SCI break characters Address: Read: Write: Reset: $0014 Bit 7 6 5 4 3 2 1 Bit 0 SCTIE TCIE SCRIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 Figure 18-10. SCI Control Register 2 (SCC2) SCTIE — SCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Reset clears the SCTIE bit.
TE — Transmitter Enable Bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the PTE0/TxD pin. If software clears the TE bit, the transmitter completes any transmission in progress before the PTE0/TxD returns to the idle condition (logic 1). Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted. Reset clears the TE bit.
SBK — Send Break Bit Setting and then clearing this read/write bit transmits a break character followed by a logic 1. The logic 1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the transmitter continuously transmits break characters with no logic 1s between them. Reset clears the SBK bit. 1 = Transmit break characters 0 = No break characters being transmitted NOTE: Do not toggle the SBK bit immediately after setting the SCTE bit.
R8 — Received Bit 8 When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character. R8 is received at the same time that the SCDR receives the other 8 bits. When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit. T8 — Transmitted Bit 8 When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted character.
ORIE — Receiver Overrun Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR. 1 = SCI error CPU interrupt requests from OR bit enabled 0 = SCI error CPU interrupt requests from OR bit disabled NEIE — Receiver Noise Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE. Reset clears NEIE.
18.9.4 SCI Status Register 1 SCI status register 1 (SCS1) contains flags to signal these conditions: • Transfer of SCDR data to transmit shift register complete • Transmission complete • Transfer of receive shift register data to SCDR complete • Receiver input idle • Receiver overrun • Noisy data • Framing error • Parity error Address: Read: $0016 Bit 7 6 5 4 3 2 1 Bit 0 SCTE TC SCRF IDLE OR NF FE PE 1 1 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 18-12.
TC — Transmission Complete Bit This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set. TC is automatically cleared when data, preamble or break is queued and ready to be sent. There may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. Reset sets the TC bit.
bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears the OR bit. 1 = Receive shift register full and SCRF = 1 0 = No receiver overrun Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing sequence.
BYTE 1 BYTE 2 BYTE 3 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 NORMAL FLAG CLEARING SEQUENCE BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1 READ SCDR BYTE 2 READ SCDR BYTE 3 BYTE 1 BYTE 2 BYTE 3 SCRF = 0 OR = 0 SCRF = 1 OR = 1 SCRF = 0 OR = 1 SCRF = 1 SCRF = 1 OR = 1 DELAYED FLAG CLEARING SEQUENCE BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 1 READ SCDR BYTE 1 READ SCDR BYTE 3 Figure 18-13.
18.9.5 SCI Status Register 2 SCI status register 2 contains flags to signal the following conditions: • Break character detected • Incoming data Address: $0017 Bit 7 6 5 4 3 2 Read: 1 Bit 0 BKF RPF 0 0 Write: Reset: 0 0 0 0 0 0 = Unimplemented Figure 18-14. SCI Status Register 2 (SCS2) BKF — Break Flag Bit This clearable, read-only bit is set when the SCI detects a break character on the PTE1/RxD pin. In SCS1, the FE and SCRF bits are also set.
18.9.6 SCI Data Register The SCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit shift registers. Reset has no effect on data in the SCI data register. Address: $0018 Bit 7 6 5 4 3 2 1 Bit 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: Unaffected by reset Figure 18-15. SCI Data Register (SCDR) R7/T7–R0/T0 — Receive/Transmit Data Bits Reading address $0018 accesses the read-only received data bits, R7:R0.
18.9.7 SCI Baud Rate Register The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter. Address: $0019 Bit 7 6 Read: Write: Reset: 0 5 4 3 2 1 Bit 0 SCP1 SCP0 R SCR2 SCR1 SCR0 0 0 0 0 0 0 R = Reserved 0 = Unimplemented Figure 18-16. SCI Baud Rate Register (SCBR) SCP1 and SCP0 — SCI Baud Rate Prescaler Bits These read/write bits select the baud rate prescaler divisor as shown in Table 18-6. Reset clears SCP1 and SCP0. Table 18-6.
Table 18-7. SCI Baud Rate Selection SCR2, SCR1, and SCR0 Baud Rate Divisor (BD) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 Use this formula to calculate the SCI baud rate: f BUS baud rate = ----------------------------------64 × PD × BD where: fBUS = bus frequency PD = prescaler divisor BD = baud rate divisor SCI_BDSRC is an input to the SCI. Normally it will be tied off low at the top level to select the bus clock as the clock source.
Table 18-8. SCI Baud Rate Selection Examples SCP1 and SCP0 Prescaler Divisor (PD) SCR2, SCR1, and SCR0 Baud Rate Divisor (BD) Baud Rate (fBUS = 4.
Advance Information — MC68HC908GP20 Section 19. System Integration Module (SIM) 19.1 Contents 19.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 19.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 291 19.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 19.3.2 Clock Startup from POR or LVI Reset. . . . . . . . . . . . . . . . 292 19.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . .
19.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 19.8.1 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . 308 19.8.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . 310 19.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . 311 19.2 Introduction This section describes the system integration module (SIM). Together with the CPU, the SIM controls all MCU activities.
MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO CGM) SIM COUNTER COP CLOCK CGMXCLK (FROM CGM) CGMOUT (FROM CGM) ÷2 CLOCK CONTROL VDD CLOCK GENERATORS INTERNAL CLOCKS INTERNAL PULLUP DEVICE RESET PIN LOGIC LVI (FROM LVI MODULE) POR CONTROL MASTER RESET CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) RESET INTERRUPT SOURCES INTERRUPT CONTROL AND PRIORIT
Addr. Register Name Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: Bit 7 6 5 4 3 2 1 R R R R R R 0 0 0 0 0 0 0 0 POR PIN COP ILOP ILAD MODRST LVI 0 1 0 0 0 0 0 0 0 R R R R R R R R BCFE R R R R R R R SBSW NOTE Bit 0 R Note: Writing a logic 0 clears SBSW.
19.3 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 19-3. This clock can come from either an external oscillator or from the on-chip PLL. (See Section 7. Clock Generator Module (CGMC).
19.3.2 Clock Startup from POR or LVI Reset When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout. 19.3.
An internal reset clears the SIM counter (see 19.5 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). (See 19.8 SIM Registers.) 19.4.1 External Pin Reset The RST pin circuit includes an internal pullup device. Pulling the asynchronous RST pin low halts all processing.
19.4.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles. See Figure 19-5. An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR. (See Figure 19-6.) NOTE: For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles during which the SIM forces the RST pin low.
19.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles. Sixty-four CGMXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, these events occur: • A POR pulse is generated. • The internal reset signal is asserted. • The SIM enables CGMOUT.
19.4.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module timeout, write any value to location $FFFF. Writing to location $FFFF clears the COP counter and bits 12 through 4 of the SIM counter.
19.4.2.5 Low-Voltage Inhibit (LVI) Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the LVITRIPF voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles. Sixty-four CGMXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the RST pin for all internal reset sources. 19.4.2.
19.5.2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask option register. If the SSREC bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32 CGMXCLK cycles.
processing can resume. Figure 19-8 shows interrupt entry timing. Figure 19-9 shows interrupt recovery timing. Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). (See Figure 19-10.
FROM RESET BREAK I BIT SET? INTERRUPT? YES NO YES I BIT SET? NO IRQ0 INTERRUPT? YES NO IRQ INTERRUPT? NO AS MANY INTERRUPTS AS EXIST ON CHIP YES STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 19-10. Interrupt Processing Advance Information 300 MC68HC908GP20 — Rev 2.
19.6.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed.
19.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does. 19.6.1.3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources.
Interrupt Status Register 1 Address: $FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read: I6 I5 I4 I3 I2 I1 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 19-12. Interrupt Status Register 1 (INT1) I6–I1 — Interrupt Flags 1–6 These flags indicate the presence of interrupt requests from the sources shown in Table 19-3.
Interrupt Status Register 3 Address: $FE06 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 I16 I15 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 19-14. Interrupt Status Register 3 (INT3) Bits 7–2 — Always read 0 I16–I15 — Interrupt Flags 16–15 These flags indicate the presence of an interrupt request from the source shown in Table 19-3. 1 = Interrupt request present 0 = No interrupt request present 19.6.
19.6.4 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the SIM break flag control register (SBFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode.
wait mode. Some modules can be programmed to be active in wait mode. Wait mode also can be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the mask option register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode.
19.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode. The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the mask option register (MOR).
STOP RECOVERY PERIOD CGMXCLK INT/BREAK IAB STOP + 2 STOP +1 STOP + 2 SP SP – 1 SP – 2 SP – 3 Figure 19-19. Stop Mode Recovery from Interrupt or Break 19.8 SIM Registers The SIM has three memory-mapped registers. Table 19-4 shows the mapping of these registers. Table 19-4. SIM Registers Address Register Access Mode $FE00 SBSR User $FE01 SRSR User $FE03 SBFCR User 19.8.
SBSW — SIM Break Stop/Wait This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic 0 to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt. 0 = Stop mode or wait mode was not exited by break interrupt. SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example of this.
19.8.2 SIM Reset Status Register This register contains six flags that show the source of the last reset provided all previous reset status bits have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register. Address: Read: $FE01 Bit 7 6 5 4 3 2 1 Bit 0 POR PIN COP ILOP ILAD MODRST LVI 0 1 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 19-21.
MODRST — Monitor Mode Entry Module Reset Bit 1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $00 after POR while IRQ = VDD 0 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI circuit 0 = POR or read of SRSR 19.8.3 SIM Break Flag Control Register The SIM break control register contains a bit that enables software to clear status bits while the MCU is in a break state.
Advance Information 312 MC68HC908GP20 — Rev 2.
Advance Information — MC68HC908GP20 Section 20. Serial Peripheral Interface Module (SPI) 20.1 Contents 20.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 20.4 Pin Name Conventions and I/O Register Addresses . . . . . . . 315 20.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315 20.5.1 Master Mode . . . . . . . . . .
20.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 20.14.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 20.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . .340 20.14.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 20.
20.4 Pin Name Conventions and I/O Register Addresses The text that follows describes the SPI. The SPI I/O pin names are SS (slave select), SPSCK (SPI serial clock), CGND (clock ground), MOSI (master out slave in), and MISO (master in/slave out). The SPI shares four I/O pins with four parallel I/O ports. The full names of the SPI I/O pins are shown in Table 20-1. The generic pin names appear in the text that follows. Table 20-1.
INTERNAL BUS TRANSMIT DATA REGISTER CGMOUT ÷ 2 FROM SIM SHIFT REGISTER 7 6 5 4 3 2 1 MISO 0 ÷2 MOSI ÷8 CLOCK DIVIDER ÷ 32 RECEIVE DATA REGISTER PIN CONTROL LOGIC ÷ 128 SPMSTR SPE CLOCK SELECT SPR1 SPSCK M CLOCK LOGIC S SS SPR0 SPMSTR RESERVED MODFEN TRANSMITTER CPU INTERRUPT REQUEST RESERVED CPHA CPOL SPWOM ERRIE SPI CONTROL SPTIE SPRIE RECEIVER/ERROR CPU INTERRUPT REQUEST DMAS SPE SPRF SPTE OVRF MODF Figure 20-2.
If a port bit is configured for input, then an internal pullup device may be enabled for that port bit. (See 16.5.3 Port C Input Pullup Enable Register.) The following paragraphs describe the operation of the SPI module. 20.5.1 Master Mode The SPI operates in master mode when the SPI master bit, SPMSTR, is set. NOTE: Configure the SPI modules as master or slave before enabling them. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI. (See 20.14.
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register. (See 20.14.2 SPI Status and Control Register.) Through the SPSCK pin, the baud rate generator of the master also controls the shift register of the slave peripheral. As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set.
When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. The slave must write to its transmit data register at least one bus cycle before the master starts the next transmission. Otherwise, the byte already in the slave shift register shifts out on the MISO pin.
The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. NOTE: Before writing to the CPOL bit or the CPHA bit, disable the SPI by clearing the SPI enable bit (SPE) . 20.6.
SPSCK CYCLE # FOR REFERENCE 1 2 3 4 5 6 7 8 MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB SPSCK; CPOL = 0 SPSCK; CPOL =1 MOSI FROM MASTER MISO FROM SLAVE MSB SS; TO SLAVE CAPTURE STROBE Figure 20-4. Transmission Format (CPHA = 0) MISO/MOSI BYTE 1 BYTE 2 BYTE 3 MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 Figure 20-5. CPHA/SS Timing When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission.
20.6.3 Transmission Format When CPHA = 1 Figure 20-6 shows an SPI transmission in which CPHA is logic 1. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave.
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the transmit data register. Therefore, the SPI data register of the slave must be loaded with transmit data before the first edge of SPSCK.
WRITE TO SPDR INITIATION DELAY BUS CLOCK MOSI MSB BIT 6 1 2 BIT 5 SPSCK CPHA = 1 SPSCK CPHA = 0 SPSCK CYCLE NUMBER 3 INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN WRITE TO SPDR BUS CLOCK EARLIEST LATEST WRITE TO SPDR SPSCK = INTERNAL CLOCK ÷ 2; 2 POSSIBLE START POINTS BUS CLOCK EARLIEST WRITE TO SPDR SPSCK = INTERNAL CLOCK ÷ 8; 8 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK ÷ 32; 32 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK ÷ 128; 128 POSSIBLE STA
20.7 Queuing Transmission Data The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready to accept new data. Write to the transmit data register only when the SPTE bit is high.
For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE is set again no more than two bus cycles after the transmit buffer empties into the shift register. This allows the user to queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur until the transmission is completed. This implies that a back-to-back write to the transmit data register is not possible. The SPTE indicates when the next write can occur. 20.
interrupts share the same CPU interrupt vector. (See Figure 20-11.) It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition. Figure 20-9 shows how it is possible to miss an overflow. The first part of Figure 20-9 shows how it is possible to read the SPSCR and SPDR to clear the SPRF without problems.
BYTE 1 SPI RECEIVE COMPLETE BYTE 2 5 1 BYTE 3 7 BYTE 4 11 SPRF OVRF READ SPSCR 2 READ SPDR 4 3 1 BYTE 1 SETS SPRF BIT. 2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. 3 6 9 8 12 10 14 13 8 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT. 9 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT. 4 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 11 BYTE 4 SETS SPRF BIT. 5 BYTE 2 SETS SPRF BIT.
MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See Figure 20-11.) It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS goes to logic 0.
slave. This happens because SS at logic 0 indicates the start of the transmission (MISO driven out with the value of MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and then later unselected with no transmission occurring. Therefore, MODF does not occur since a transmission was never begun. In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU interrupt request if the ERRIE bit is set. The MODF bit does not clear the SPE bit or reset the SPI in any way.
Reading the SPI status and control register with SPRF set and then reading the receive data register clears SPRF. The clearing mechanism for the SPTE flag is always just a write to the transmit data register. The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU interrupt requests, provided that the SPI is enabled (SPE = 1).
The following sources in the SPI status and control register can generate CPU interrupt requests: • SPI receiver full bit (SPRF) — The SPRF bit becomes set every time a byte transfers from the shift register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, SPRF generates an SPI receiver/error CPU interrupt request. • SPI transmitter empty (SPTE) — The SPTE bit becomes set every time a byte transfers from the transmit data register to the shift register.
By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be disabled by a mode fault occuring in an SPI that was configured as a master with the MODFEN bit set. 20.11 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 20.11.1 Wait Mode The SPI module remains active after the execution of a WAIT instruction.
20.12 SPI During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See Section 19. System Integration Module (SIM).) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit.
The SPI has limited inter-integrated circuit (I2C) capability (requiring software support) as a master in a single-master environment. To communicate with I2C peripherals, MOSI becomes an open-drain output when the SPWOM bit in the SPI control register is set. In I2C communication, the MOSI and MISO pins are connected to a bidirectional pin from the I2C peripheral and through a pullup resistor to VDD. 20.13.1 MISO (Master In/Slave Out) MISO is one of the two SPI module pins that transmits serial data.
20.13.3 SPSCK (Serial Clock) The serial clock synchronizes data transmission between master and slave devices. In a master MCU, the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles. When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I/O port. 20.13.
When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to prevent multiple masters from driving MOSI and SPSCK. (See 20.8.2 Mode Fault Error.) For the state of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data direction register of the shared I/O port.
20.14 I/O Registers Three registers control and monitor SPI operation: • SPI control register (SPCR) • SPI status and control register (SPSCR) • SPI data register (SPDR) 20.14.
DMAS —DMA Select Bit This read only bit has no effect on this version of the SPI. This bit always reads as a 0. 0 = SPRF DMA and SPTE DMA service requests disabled (SPRF CPU and SPTE CPU interrupt requests enabled) SPMSTR — SPI Master Bit This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR bit. 1 = Master mode 0 = Slave mode CPOL — Clock Polarity Bit This read/write bit determines the logic state of the SPSCK pin between transmissions.
SPTIE— SPI Transmit Interrupt Enable This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte transfers from the transmit data register to the shift register. Reset clears the SPTIE bit. 1 = SPTE CPU interrupt requests enabled 0 = SPTE CPU interrupt requests disabled 20.14.
SPRF — SPI Receiver Full Bit This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also. During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Reset clears the SPRF bit.
SPTE — SPI Transmitter Empty Bit This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. SPTE generates an SPTE CPU interrupt request or an SPTE DMA service request if the SPTIE bit in the SPI control register is set also. NOTE: Do not write to the SPI data register unless the SPTE bit is high. During an SPTE CPU interrupt, the CPU clears the SPTE bit by writing to the transmit data register. Reset sets the SPTE bit.
Table 20-4. SPI Master Baud Rate Selection SPR1 and SPR0 Baud Rate Divisor (BD) 00 2 01 8 10 32 11 128 Use this formula to calculate the SPI baud rate: CGMOUT Baud rate = -------------------------2 × BD where: CGMOUT = base clock output of the clock generator module (CGM) BD = baud rate divisor 20.14.3 SPI Data Register The SPI data register consists of the read-only receive data register and the write-only transmit data register.
Advance Information 344 MC68HC908GP20 — Rev 2.
Advance Information — MC68HC908GP20 Section 21. Timebase Module (TBM) 21.1 Contents 21.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346 21.5 Timebase Register Description. . . . . . . . . . . . . . . . . . . . . . . . 347 21.6 Interrupts. . . . . . . . . . . . .
21.4 Functional Description NOTE: This module is designed for a 32.768-kHz oscillator. This module can generate a periodic interrupt by dividing the crystal frequency, CGMXCLK. The counter is initialized to all 0s when TBON bit is cleared. The counter, shown in Figure 21-1, starts counting when the TBON bit is set. When the counter overflows at the tap selected by TBR2:TBR0, the TBIF bit gets set. If the TBIE bit is set, an interrupt request is sent to the CPU.
21.5 Timebase Register Description The timebase has one register, the TBCR, which is used to enable the timebase interrupts and set the rate. Address: $001C Bit 7 Read: TBIF Write: Reset: 6 5 4 TBR2 TBR1 TBR0 0 0 0 0 3 0 TACK 2 1 Bit 0 TBIE TBON TBTST* 0 0 0 0 * PTM test mode = Unimplemented Figure 21-2. Timebase Control Register (TBCR) TBIF — Timebase Interrupt Flag This read-only flag bit is set when the timebase counter has rolled over.
NOTE: Do not change TBR2–TBR0 bits while the timebase is enabled (TBON = 1). TACK— Timebase ACKnowledge The TACK bit is a write-only bit and always reads as 0. Writing a logic 1 to this bit clears TBIF, the timebase interrupt flag bit. Writing a logic 0 to this bit has no effect. 1 = Clear timebase interrupt flag 0 = No effect TBIE — Timebase Interrupt Enabled This read/write bit enables the timebase interrupt when the TBIF bit becomes set. Reset clears the TBIE bit.
21.7 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 21.7.1 Wait Mode The timebase module remains active after execution of the WAIT instruction. In wait mode, the timebase register is not accessible by the CPU. If the timebase functions are not required during wait mode, reduce the power consumption by stopping the timebase before enabling the WAIT instruction. 21.7.
Advance Information 350 MC68HC908GP20 — Rev 2.
Advance Information — MC68HC908GP20 Section 22. Timer Interface Module (TIM) 22.1 Contents 22.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 22.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 22.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 22.5.1 TIM Counter Prescaler . .
22.2 Introduction This section describes the timer interface (TIM) module. The TIM is a 2channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 22-1 is a block diagram of the TIM. This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2. 22.
22.4 Pin Name Conventions The text that follows describes both timers, TIM1 and TIM2. The TIM input/output (I/O) pin names are T[1,2]CH0 (timer channel 0) and T[1,2]CH1 (timer channel 1), where “1” is used to indicate TIM1 and “2” is used to indicate TIM2. The two TIMs share four I/O pins with four port D I/O port pins. The full names of the TIM I/O pins are listed in Table 22-1. The generic pin names appear in the text that follows. Table 22-1.
The two TIM channels (per timer) are programmable independently as input capture or output compare channels. If a channel is configured as input capture, then an internal pullup device may be enabled for that channel. (See 16.5.3 Port C Input Pullup Enable Register.
Addr.
Addr.
Addr.
22.5.3 Output Compare With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. 22.5.4 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 22.5.3 Output Compare.
22.5.5 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin.
The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is $000. See 22.10.1 TIM Status and Control Register.
during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: NOTE: • When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine.
buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE: In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered PWM signals. 22.5.
5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP. Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows.
22.7 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 22.7.1 Wait Mode The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction.
I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. 22.9 I/O Signals Port D shares four of its pins with the TIM.
22.10.1 TIM Status and Control Register The TIM status and control register (TSC): • Enables TIM overflow interrupts • Flags TIM overflows • Stops the TIM counter • Resets the TIM counter • Prescales the TIM counter clock Address: T1SC, $0020 and T2SC, $002B Bit 7 Read: TOF Write: 0 Reset: 0 6 5 TOIE TSTOP 0 1 4 3 0 0 TRST 0 0 2 1 Bit 0 PS2 PS1 PS0 0 0 0 = Unimplemented Figure 22-4.
TSTOP — TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active NOTE: Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. TRST — TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers.
22.10.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
22.10.3 TIM Counter Modulo Registers The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
22.10.4 TIMA Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
22.10.
CHxF — Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. When TIM CPU interrupt requests are enabled (CHxIE:DMAxS = 1:0), clear CHxF by reading TIM channel x status and control register with CHxF set and then writing a logic 0 to CHxF.
Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA — Mode Select Bit A When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 22-3. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin. See Table 22-3. Reset clears the MSxA bit.
Table 22-3.
CHxMAX — Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 0, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 2213 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared. OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW PERIOD PTEx/TCHx OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE CHxMAX Figure 22-13.
Address: T1CH0H, $0026 and T2CH0H, $0031 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Reset: Indeterminate after reset Figure 22-14. TIM Channel 0 Register High (TCH0H) Address: T1CH0L, $0027 and T2CH0L $0032 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Reset: Indeterminate after reset Figure 22-15.
Advance Information — MC68HC908GP20 Section 23. Preliminary Electrical Specifications 23.1 Contents 23.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 23.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 378 23.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 379 23.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 23.6 5.
23.2 Introduction This section contains electrical and timing specifications. These values are design targets and have not yet been fully tested. 23.3 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to 23.6 5.0-V DC Electrical Characteristics for guaranteed operating conditions.
23.4 Functional Operating Range Characteristic Symbol Value Unit TA –40 to +85 °C VDD 3.0 ±10% 5.0 ±10% V Symbol Value Unit Thermal resistance PDIP (40-pin) QFP (44-pin) θJA 60 95 °C/W I/O pin power dissipation PI/O User-Determined W Power dissipation(1) PD PD = (IDD × VDD) + PI/O = K/(TJ + 273 °C) W Constant(2) K PJ x (TA + 273 °C) + PD2 × θJA W/°C Average junction temperature TJ TA + (PD × θJA) °C TJM 125 °C Operating temperature range Operating voltage range 23.
23.6 5.0-V DC Electrical Characteristics Symbol Min Typ(2) Max Unit VOH VOH VOH IOH1 VDD – 0.8 VDD – 1.5 VDD – 0.8 — — — — — — — — 50 V V V mA IOH2 — — 50 mA IOHT — — 100 mA VOL VOL VOL IOL1 — — — — — — — — 0.4 1.5 1.0 50 V V V mA IOL2 — — 50 mA IOLT — — 100 mA Input high voltage All ports, IRQs, RESET, OSC1 VIH 0.7 x VDD — VDD V Input low voltage All ports, IRQs, RESET, OSC1 VIL VSS — 0.
Symbol Min Typ(2) Max Unit Low-voltage inhibit, trip falling voltage – target VTRIPF 4.13 4.3 4.35 V Low-voltage inhibit, trip rising voltage – target VTRIPR 4.23 4.4 4.45 V Low-voltage inhibit reset/recover hysteresis – target (VTRIPF + VHYS = VTRIPR) VHYS — 100 — mV POR rearm voltage(8) VPOR 0 — 100 mV POR reset voltage(9) VPORRST 0 700 800 mV RPOR 0.035 — — V/ms Characteristic(1) POR rise time ramp rate(10) Notes: 1. VDD = 5.
23.7 3.0-V DC Electrical Characteristics Symbol Min Typ(2) Max Unit VOH VOH VOH IOH1 VDD – 0.3 VDD – 1.0 VDD – 0.5 — — — — — — — — 30 V V V mA IOH2 — — 30 mA IOHT — — 60 mA VOL VOL VOL IOL1 — — — — — — — — 0.3 1.0 0.8 30 V V V mA IOL2 — — 30 mA IOLT — — 60 mA Input high voltage All ports, IRQs, RESET, OSC1 VIH 0.7 x VDD — VDD V Input low voltage All ports, IRQs, RESET, OSC1 VIL VSS — 0.
Symbol Min Typ(2) Max Unit Low-voltage inhibit, trip falling voltage – target VTRIPF 2.5 2.6 2.63 V Low-voltage inhibit, trip rising voltage – target VTRIPR 2.6 2.66 2.73 V Low-voltage inhibit reset/recover hysteresis – target (VTRIPF + VHYS = VTRIPR) VHYS — 60 — mV POR rearm voltage(8) VPOR 0 — 100 mV POR reset voltage(9) VPORRST 0 700 800 mV RPOR 0.02 — — V/ms Characteristic(1) POR rise time ramp rate(10) Notes: 1. VDD = 3.
23.8 5.0-V Control Timing Characteristic(1) Symbol Min Max Unit Frequency of operation(2) Crystal option External clock option(3) fosc 32 dc(4) 100 32.8 kHz MHz Internal operating frequency fop — 8.
23.9 3.0-V Control Timing Characteristic(1) Symbol Min Max Unit Frequency of operation(2) Crystal option External clock option(3) fosc 32 dc(4) 100 16.4 kHz MHz Internal operating frequency fop — 4.
23.10 Output High-Voltage Characteristics 0 –5 –40 25 85 IOH (mA) –10 –15 –20 –25 –30 –35 3 3.5 4 4.5 VOH (V) VOH < VDD –0.8 V @ IOH = –2.0 mA VOH < VDD –1.5 V @ IOH = –10.0 mA Figure 23-1. Typical High-Side Driver Characteristics – Ports PTA7–PTA0, PTB7–PTB0, PTC6–PTC5, PTD7–PTD0, and PTE1–PTE0 (VDD = 4.5 Vdc) 0 IOH (mA) –5 –10 –40 25 85 –15 –20 –25 1 1.2 1.4 1.6 1.8 VOH (V) 2 2.2 2.4 VOH < VDD –0.3 V @ IOH = –0.6 mA VOH < VDD –1.0 V @ IOH = –4.0 mA Figure 23-2 .
23.11 Output Low-Voltage Characteristics 35 IOL (mA) 30 25 –40 25 85 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 VOL(V) VOL < 0.4 V @ IOL = 1.6 mA VOL < 1.5 V @ IOL = 10.0 mA IOL (mA) Figure 23-3. Typical Low-Side Driver Characteristics – Ports PTA7–PTA0, PTB7–PTB0, PTC6–PTC5, PTD7–PTD0, and PTE1–PTE0 (VDD = 4.5 Vdc) 20 18 16 14 12 10 8 6 4 2 0 –40 25 85 0 0.2 0.4 0.6 0.8 VOL (V) 1 1.2 1.4 VOL < 0.3 V @ IOL = 0.5 mA VOL < 1.0V @ IOL = 6.0 mA Figure 23-4.
IOL (mA) 70 60 50 40 30 20 10 0 –40 25 85 0 0.2 0.4 0.6 0.8 VOL (V) 1 1.2 1.4 VOL < 1.0 V @ IOL = 15 mA IOL (mA) Figure 23-5. Typical Low-Side Driver Characteristics for Higher Current Drive – Ports PTC4–PTC0 (VDD = 4.5 Vdc) 40 35 30 25 -40 25 85 20 15 10 5 0 0 0.2 0.4 0.6 0.8 VOL (V) 1 1.2 1.4 VOL < 0.8 V @ IOL = 10 mA Figure 23-6. Typical Low-Side Driver Characteristics for Higher Current Drive – Ports PTC4–PTC0 (VDD = 2.7 Vdc) Advance Information 388 MC68HC908GP20 — Rev 2.
23.12 Typical Supply Currents 30 25 IDD (mA) 20 15 10 5.5 V 3.3 V 5 0 0 1 2 3 4 5 fbus (MHz) 6 7 8 9 Figure 23-7. Typical Operating IDD with All Modules Turned On (–40 °C to 85 °C) 5.0 4.5 4.0 IDD (mA) 3.5 3.0 2.5 2.0 1.5 1.0 5.5 V 3.3 V 0.5 0 0 1 2 3 4 fbus (MHz) 5 6 7 8 Figure 23-8. Typical Wait Mode IDD with TBM Enabled, LVI Disabled, and PLL Disabled (–40 °C to 85 °C) MC68HC908GP20 — Rev 2.
6 5 IDD (mA) 4 3 2 5.5 V 3.3 V 1 0 0 1 2 3 4 5 fbus (MHz) 6 7 8 9 Figure 23-9. Typical Wait Mode IDD, with LVI and TBM Enabled, PLL Disabled (–40 °C to 85 °C) Advance Information 390 MC68HC908GP20 — Rev 2.
23.13 ADC Characteristics Characteristic(1) Symbol Min Max Unit Comments Supply voltage VDDAD 2.7 (VDD min) 5.5 (VDD max) V VDDAD should be tied to the same potential as VDD via separate traces. Input voltages VADIN VREFH 0 1.5 VDDAD VDDAD V VADIN <= VREFH Resolution BAD 8 8 Bits Absolute accuracy (VREFL = 0 V, VDDAD = VREFH = 5 V ± 10%) AAD ± 1/2 ±1 LSB Includes quantization ADC internal clock fADIC 0.5 1.
23.14 5.
23.15 3.
SS INPUT SS PIN OF MASTER HELD HIGH 1 SPSCK OUTPUT CPOL = 0 NOTE SPSCK OUTPUT CPOL = 1 NOTE 5 4 5 4 6 MISO INPUT MSB IN BITS 6–1 11 MOSI OUTPUT MASTER MSB OUT 7 LSB IN 10 11 BITS 6–1 MASTER LSB OUT Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
SS INPUT 3 1 SPSCK INPUT CPOL = 0 5 4 2 SPSCK INPUT CPOL = 1 5 4 9 8 MISO INPUT SLAVE MSB OUT 6 MOSI OUTPUT BITS 6–1 7 NOTE 11 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN Note: Not defined but normally MSB of character just received a) SPI Slave Timing (CPHA = 0) SS INPUT 1 SPSCK INPUT CPOL = 0 5 4 2 3 SPSCK INPUT CPOL = 1 8 MISO OUTPUT 5 4 10 NOTE MOSI INPUT 9 SLAVE MSB OUT 6 7 BITS 6–1 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN Note: Not defined but normally LSB of char
23.16 Timer Interface Module Characteristics Characteristic Input capture pulse width Symbol Min Max Unit tTIH, tTIL 1 — tcyc 23.17 Clock Generation Module Characteristics 23.17.1 CGM Component Specifications Characteristic Symbol Min Typ Max Unit fXCLK 30 32.
23.17.2 CGM Electrical Specifications Description Symbol Min Typ Max Unit VDD 2.7 — 5.5 V T –40 25 130 o Crystal reference frequency fRCLK 30 32.768 100 kHz Range nominal multiplier fNOM — 38.4 — kHz VCO center-of-range frequency(1) fVRS 38.4 k — 40.0 M Hz Medium-voltage VCO center-of-range frequency(2) fVRS 38.4 k — 40.
23.18 Memory Characteristics Characteristic Symbol Min Typ Max Unit VRDR 1.3 — — V FLASH pages per row — 8 — 8 Pages FLASH bytes per page — 8 — 8 Bytes 32 k — 8.4 M Hz RAM data retention voltage (1) FLASH read bus clock frequency fRead FLASH charge pump clock frequency (See 11.5.1 FLASH Charge Pump Frequency Control.) fPump(2) 1.8 — 2.
Advance Information — MC68HC908GP20 Section 24. Mechanical Specifications 24.1 Contents 24.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 24.3 40-Pin Plastic Dual In-Line Package (DIP) . . . . . . . . . . . . . . . 400 24.4 44-Pin Plastic Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . . 401 24.
24.3 40-Pin Plastic Dual In-Line Package (DIP) 40 NOTES: 1. POSITION TOLERANCE OF LEADS (D), SHALL BEWITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITIONS, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 21 B 1 20 L A C N J H Advance Information 400 G F D K SEATING PLANE M DIM MILLIMETERS MIN MAX MIN INCHES MAX A B C D F G H J K L M N 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.
24.4 44-Pin Plastic Quad Flat Pack (QFP) S 0.20 (0.008) M T L-M S N S -L-, -M-, -N- A 0.20 (0.008) M H L-M S N S 0.05 (0.002) L-M PIN 1 IDENT 44 J1 34 33 -M- VIEW Y G 11 40X V 0.20 (0.008) M T L-M S N S -L- 0.05 (0.002) N J1 B 0.20 (0.008) M H L-M S N S 1 VIEW Y 3 PL F PLATING BASE METAL J B1 D 0.20 (0.008) M T L-M S N S 23 12 G 22 SECTION J1-J1 44 PL -N- M VIEW P C E -H- 0.01 (0.004) W Y q1 R DATUM PLANE -H- R K A1 C1 VIEW P MC68HC908GP20 — Rev 2.
Advance Information 402 MC68HC908GP20 — Rev 2.
Advance Information — MC68HC908GP20 Section 25. Ordering Information 25.1 Contents 25.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 25.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 25.2 Introduction This section contains ordering numbers for the MC68HC908GP20. 25.3 MC Order Numbers Table 25-1.
Advance Information 404 MC68HC908GP20 — Rev 2.
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