Datasheet

ManualsBrandsNXP ManualsEmbedded Processors & ControllersSingle NAND Gate 74AHC TSSOP 6.5ns

1. General description

74AHC1G00 and 74AHCT1G00 are high-speed Si-gate CMOS devices. They provide a

2-input NAND function.

The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.

The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.

2. Features

n Symmetrical output impedance

n High noise immunity

n Low power dissipation

n Balanced propagation delays

n SOT353-1 and SOT753 package options

n ESD protection:

u HBM JESD22-A114E: exceeds 2000 V

u MM JESD22-A115-A: exceeds 200 V

u CDM JESD22-C101C: exceeds 1000 V

n Speciﬁed from −40 °C to +125 °C

3. Ordering information

74AHC1G00; 74AHCT1G00

2-input NAND gate

Rev. 06 — 30 May 2007 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74AHC1G00GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package;

5 leads; body width 1.25 mm

SOT353-1

74AHCT1G00GW

74AHC1G00GV −40 °C to +125 °C SC-74A plastic surface-mounted package; 5 leads SOT753

74AHCT1G00GV

Summary of content (11 pages)

PAGE 1
74AHC1G00; 74AHCT1G00 2-input NAND gate Rev. 06 — 30 May 2007 Product data sheet 1. General description 74AHC1G00 and 74AHCT1G00 are high-speed Si-gate CMOS devices. They provide a 2-input NAND function. The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V. The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V. 2.
PAGE 2
74AHC1G00; 74AHCT1G00 NXP Semiconductors 2-input NAND gate 4. Marking Table 2. Marking codes Type number Marking 74AHC1G00GW AA 74AHC1G00GV A00 74AHCT1G00GW CA 74AHCT1G00GV C00 5. Functional diagram B 1 B 2 A 1 Y & 4 4 Y 2 Fig 1. Logic symbol A mna098 mna097 Fig 2. IEC logic symbol mna099 Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 74AHC1G00 74AHCT1G00 B 1 A 2 GND 3 5 VCC 4 Y 001aaf092 Fig 4. Pin configuration 6.2 Pin description Table 3.
PAGE 3
74AHC1G00; 74AHCT1G00 NXP Semiconductors 2-input NAND gate 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level Inputs Output A B Y L L H L H H H L H H H L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Min Max Unit VCC supply voltage Conditions −0.5 +7.0 V VI input voltage −0.5 +7.0 V IIK input clamping current VI < −0.
PAGE 4
74AHC1G00; 74AHCT1G00 NXP Semiconductors 2-input NAND gate 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V For type 74AHC1G00 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage VCC = 2.
PAGE 5
74AHC1G00; 74AHCT1G00 NXP Semiconductors 2-input NAND gate Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 1.0 - 10 - 40 µA ∆ICC additional per input pin; VI = 3.4 V; supply current other inputs at VCC or GND; IO = 0 A; VCC = 5.5 V - - 1.35 - 1.5 - 1.
PAGE 6
74AHC1G00; 74AHCT1G00 NXP Semiconductors 2-input NAND gate 12. Waveforms A, B input VM tPHL tPLH VM Y output mna106 Measurement points are given in Table 9. Fig 5. The inputs (A and B) to output (Y) propagation delays Table 9. Measurement point Type Input Output VI VM VM 74AHC1G00 GND to VCC 0.5 × VCC 0.5 × VCC 74AHCT1G00 GND to 3.0 V 1.5 V 0.5 × VCC VCC PULSE GENERATOR VI VO DUT RT CL mna101 Test data is given in Table 8.
PAGE 7
4AHC1G00; 74AHCT1G00 NXP Semiconductors 2-input NAND gate 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm E D SOT353-1 A X c y HE v M A Z 5 4 A2 A (A3) A1 θ 1 Lp 3 L e w M bp detail X e1 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) θ mm 1.1 0.1 0 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.
PAGE 8
74AHC1G00; 74AHCT1G00 NXP Semiconductors 2-input NAND gate Plastic surface-mounted package; 5 leads SOT753 D E B y A X HE 5 v M A 4 Q A A1 c 1 2 3 Lp detail X bp e w M B 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.100 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.
PAGE 9
74AHC1G00; 74AHCT1G00 NXP Semiconductors 2-input NAND gate 14. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 11.
PAGE 10
74AHC1G00; 74AHCT1G00 NXP Semiconductors 2-input NAND gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 11
NXP Semiconductors 74AHC1G00; 74AHCT1G00 2-input NAND gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information .