Datasheet

ManualsBrandsNXP ManualsEmbedded Processors & ControllersSingle Inverter 74AHC TSSOP 4.9ns

1. General description

The 74AHC1GU04 is a high-speed Si-gate CMOS device. It provides an inverting single

stage function.

2. Features

n Symmetrical output impedance

n High noise immunity

n Low power dissipation

n Balanced propagation delays

n ESD protection:

u HBM JESD22-A114E: exceeds 2000 V

u MM JESD22-A115-A: exceeds 200 V

u CDM JESD22-C101C: exceeds 1000 V

n Speciﬁed from −40 °C to +125 °C

3. Ordering information

4. Marking

74AHC1GU04

Inverter

Rev. 05 — 10 July 2007 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74AHC1GU04GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package;

5 leads; body width 1.25 mm

SOT353-1

74AHC1GU04GV −40 °C to +125 °C SC-74A plastic surface-mounted package; 5 leads SOT753

Table 2. Marking codes

Type number Marking

74AHC1GU04GW AD

74AHC1GU04GV AU4

Summary of content (12 pages)

PAGE 1
74AHC1GU04 Inverter Rev. 05 — 10 July 2007 Product data sheet 1. General description The 74AHC1GU04 is a high-speed Si-gate CMOS device. It provides an inverting single stage function. 2. Features n n n n n Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays ESD protection: u HBM JESD22-A114E: exceeds 2000 V u MM JESD22-A115-A: exceeds 200 V u CDM JESD22-C101C: exceeds 1000 V n Specified from −40 °C to +125 °C 3. Ordering information Table 1.
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74AHC1GU04 NXP Semiconductors Inverter 5. Functional diagram 2 A Y 4 1 2 mna044 mna043 Fig 1. Logic symbol 4 A Y mna045 Fig 2. IEC logic symbol Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 74AHC1GU04 n.c. 1 A 2 GND 3 5 VCC 4 Y 001aaf099 Fig 4. Pin configuration 6.2 Pin description Table 3. Pin description Symbol Pin Description n.c. 1 not connected A 2 data input GND 3 ground (0 V) Y 4 data output VCC 5 supply voltage 7.
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74AHC1GU04 NXP Semiconductors Inverter 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current IO output current VI < −0.5 V Min Max Unit −0.5 +7.0 V −20 - mA −0.5 +7.0 V VO < −0.5 V or VO > VCC + 0.5 V - ±20 mA −0.5 V < VO < VCC + 0.
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74AHC1GU04 NXP Semiconductors Inverter Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol VOH VOL Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = −50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = −50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = −4.0 mA; VCC = 3.0 V 2.58 - - 2.
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74AHC1GU04 NXP Semiconductors Inverter fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts. 12. Waveforms VM(1) A input VCC tPHL tPLH PULSE GENERATOR VI CL 50 pF RT VM(1) Y output VO DUT mna046 mna034 VM = 0.5 × VCC; VI = GND to VCC. Test data is given in Table 8. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
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74AHC1GU04 NXP Semiconductors Inverter mna399 6 50 VO (V) ICC (mA) 40 VO Rbias = 560 kΩ VCC 30 3 0.47 µF 20 input output 100 µF VI (f = 1 kHz) ID (drain current) 10 A IO GND mna050 0 0 0 2 4 VI (V) 6 Fig 9. VCC = 5.5 V; IO = 0 A Fig 10. Test set-up for measuring forward transconductance gfs = ∆IO/∆VI at VO is constant mna400 40 gfs (mA/V) 30 20 10 0 0 2 4 VCC (V) 6 Fig 11. Typical forward transconductance gfs as a function of the supply voltage at Tamb = 25 °C 14.
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4AHC1GU04 NXP Semiconductors Inverter R2 R1 VCC 1 µF R2 R1 U04 U04 C1 ZL C2 out mna052 mna053 Maximum Vo(p-p) = VCC − 1.5 V centered at 0.5 × VCC. C1 = 47 pF (typ.) G ol G v = – --------------------------------------R1 1 + ------- ( 1 + G ol ) R2 R1 = 1 MΩ to 10 MΩ (typ.) C2 = 22 pF (typ.) R2 optimum value depends on the frequency and required stability against changes in VCC or average minimum ICC (ICC is typically 2 mA at VCC = 3 V and f = 1 MHz).
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74AHC1GU04 NXP Semiconductors Inverter 15. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm E D SOT353-1 A X c y HE v M A Z 5 4 A2 A (A3) A1 θ 1 Lp 3 L e w M bp detail X e1 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) θ mm 1.1 0.1 0 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.425 0.46 0.21 0.3 0.
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74AHC1GU04 NXP Semiconductors Inverter Plastic surface-mounted package; 5 leads SOT753 D E B y A X HE 5 v M A 4 Q A A1 c 1 2 3 Lp detail X bp e w M B 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.100 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.
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74AHC1GU04 NXP Semiconductors Inverter 16. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 17. Revision history Table 12.
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74AHC1GU04 NXP Semiconductors Inverter 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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74AHC1GU04 NXP Semiconductors Inverter 20. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . .