INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT191 Presettable synchronous 4-bit binary up/down counter Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter Overflow/underflow indications are provided by two types of outputs, the terminal count (TC) and ripple clock (RC). The TC output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches “15” in the count-up-mode. The TC output will remain HIGH until a state change occurs, either by counting or presetting, or until U/D is changed.
Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT191 QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay CP to Qn fmax maximum clock frequency CI input capacitance CPD power dissipation capacitance per package CL = 15 pF; VCC = 5 V notes 1 and 2 Notes 1.
Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT191 PIN DESCRIPTION PIN NO.
Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT191 Fig.4 Functional diagram.
Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT191 Fig.5 N-stage ripple counter using ripple clock. Fig.6 Synchronous n-stage counter using ripple carry/borrow. Fig.7 Synchronous n-stage counter with parallel gated carry/borrow.
Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT191 Sequence Load (preset) to binary thirteen; count up to fourteen, fifteen, zero, one and two; inhibit; count down to one, zero, fifteen, fourteen and thirteen. Fig.8 Typical load, count and inhibit sequence. Fig.9 Logic diagram.
Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT191 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 min. typ. max. min. −40 to +125 max. min. max.
Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT191 Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. typ. max. −40 to +85 min. −40 to +125 max. min. UNIT V CC (V) WAVEFORMS max. trem removal time PL to CP 35 7 6 8 3 2 45 9 8 55 11 9 ns 2.0 4.5 6.0 Fig.15 tsu set-up time U/D to CP 205 41 35 50 18 14 255 51 43 310 62 53 ns 2.0 4.5 6.0 Fig.
Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT191 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT191 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 min. typ. max. min. −40 to +125 max. min. max. UNIT V CC (V) WAVEFORMS tPHL/ tPLH propagation delay CP to Qn 26 48 60 72 ns 4.5 Fig.10 tPHL/ tPLH propagation delay CP to TC 32 51 64 77 ns 4.5 Fig.
Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT191 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.
Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT191 (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.13 Waveforms showing the input (PL) to output (Qn) propagation delays. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.14 Waveforms showing the up/down count input (U/D) to terminal count and ripple clock output (TC, RC) propagation delays. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.
Philips Semiconductors Product specification Presettable synchronous 4-bit binary up/down counter 74HC/HCT191 The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.16 Waveforms showing the set-up and hold times from the parallel load input (PL) to the data input (Dn). The shaded areas indicate when the input is permitted to change for predictable output performance.
