Datasheet

ManualsBrandsNXP ManualsEmbedded Processors & ControllersDual JK Flip-Flop with Clear DIP 77MHz

1. General description

The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power

Schottky TTL (LSTTL). The 74HC73 is speciﬁed in compliance with JEDEC

standard no. 7A.

The 74HC is a dual negative-edge triggered JK ﬂip-ﬂop featuring individual J, K, clock

(nCP) and reset (nR) inputs; also complementary nQ and nQ outputs.

The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock

transition for predictable operation.

The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock

and data inputs, forcing the nQ output LOW and the nQ output HIGH.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock

rise and fall times.

2. Features

■ Low-power dissipation

■ Complies with JEDEC standard no. 7A

■ ESD protection:

◆ HBM EIA/JESD22-A114-B exceeds 2000 V

◆ MM EIA/JESD22-A115-A exceeds 200 V.

■ Multiple package options

■ Speciﬁed from −40 °Cto+80°C and from −40 °C to +125 °C.

74HC73

Dual JK ﬂip-ﬂop with reset; negative-edge trigger

Rev. 03 — 12 November 2004 Product data sheet

Summary of content (22 pages)

PAGE 1
74HC73 Dual JK flip-flop with reset; negative-edge trigger Rev. 03 — 12 November 2004 Product data sheet 1. General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. The 74HC is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary nQ and nQ outputs.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. Symbol Parameter Conditions Min tPHL, tPLH propagation delay CL = 15 pF; VCC = 5 V - Unit - nCP to nQ - 16 - ns - 16 - ns nR to nQ, nQ - 15 - ns - 77 - MHz - 3.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger 5. Functional diagram 14 1J 1 1CP 3 1K J Q 1Q 12 FF1 CP Q K 1Q 13 R 2 1R 7 2J 5 2CP 10 2K J Q 2Q 9 FF2 CP Q K 2Q 8 R 6 2R 001aab981 Fig 1. Functional diagram 4 14 7 1J 2J 1 1CP 5 2CP 3 10 1K 2K 1Q 12 Q 2Q 9 J 1 3 2 FF CP Q K 1Q 13 2Q 8 R 1R 2R 2 6 7 5 10 6 1J 12 C1 1K 13 R 1J 9 C1 1K 8 R 001aab979 001aab980 Fig 2. Logic symbol 9397 750 13815 Product data sheet Fig 3.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger C C C C K Q J C C C C R Q C CP 001aab982 C Fig 4. Logic diagram (one flip-flop) 6. Pinning information 6.1 Pinning 1CP 1 14 1J 1R 2 13 1Q 1K 3 12 1Q VCC 4 2CP 5 2R 6 9 2Q 2J 7 8 2Q 73 11 GND 10 2K 001aab978 Fig 5. Pin configuration 6.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger Table 3: Pin description …continued Symbol Pin Description GND 11 ground (0 V) 1Q 12 true flip-flop 1 output 1Q 13 complement flip-flop 1 output 1J 14 synchronous J input for flip-flop 1 7. Functional description 7.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger 9. Recommended operating conditions Table 6: Recommended operating conditions Symbol Parameter VCC Min Typ Max Unit supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage tr, tf input rise and fall times except for nCP Tamb Conditions 0 - VCC V VCC = 2.0 V - - 1000 ns VCC = 4.5 V - 6.0 500 ns VCC = 6.0 V - - 400 ns −40 - +125 °C ambient temperature 10.
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4HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = −20 µA; VCC = 2.0 V 1.9 - - V IO = −20 µA; VCC = 4.5 V 4.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = −20 µA; VCC = 2.0 V 1.9 - - V IO = −20 µA; VCC = 4.5 V 4.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger 11. Dynamic characteristics Table 8: Dynamic characteristics GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 8. Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V - 52 160 ns VCC = 4.5 V - 19 32 ns VCC = 6.0 V - 15 27 ns VCC = 5.0 V; CL = 15 pF - 16 - ns VCC = 2.0 V - 52 160 ns VCC = 4.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger Table 8: Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 8. Symbol Parameter Conditions th hold time nJ, nK to nCP see Figure 6 fmax maximum clock frequency Min Typ Max Unit VCC = 2.0 V 3 −8 - ns VCC = 4.5 V 3 −3 - ns VCC = 6.0 V 3 −2 - ns VCC = 2.0 V 6.0 23 - MHz VCC = 4.5 V 30 70 - MHz VCC = 6.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger Table 8: Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 8. Symbol Parameter Conditions tsu set-up time nJ, nK to nCP see Figure 6 th fmax hold time nJ, nK to nCP maximum clock frequency Min Typ Max Unit VCC = 2.0 V 100 - - ns VCC = 4.5 V 20 - - ns VCC = 6.0 V 17 - - ns VCC = 2.0 V 3 - - ns VCC = 4.5 V 3 - - ns VCC = 6.0 V 3 - - ns VCC = 2.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger Table 8: Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 8. Symbol Parameter Conditions trem removal time nR to nCP see Figure 7 set-up time nJ, nK to nCP tsu hold time nJ, nK to nCP th maximum clock frequency fmax [1] Min Typ Max Unit VCC = 2.0 V 120 - - ns VCC = 4.5 V 24 - - ns VCC = 6.0 V 20 - - ns VCC = 2.0 V 120 - - ns VCC = 4.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger 12. Waveforms nJ, nK input VM th tsu 1/f max th tsu VM nCP input tW tPHL tPLH VM nQ output tTHL nQ output tTLH VM tTLH tTHL tPLH tPHL 001aab983 The shaded areas indicate when the input is permitted to change for predictable output performance. VM = 0.5 × VI. Fig 6.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger VCC PULSE GENERATOR VI VO D.U.T. RT CL mna101 Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig 8. Load circuitry for switching times Table 9: Test data Supply Input Load VCC VI tr, tf CL 2.0 V VCC 6 ns 50 pF 4.5 V VCC 6 ns 50 pF 6.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger 13. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger 14. Revision history Table 10: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes 74HC73_3 20041112 Product data sheet - 74HC_HCT73_CNV_2 Modifications: 9397 750 13815 • The format of this data sheet has been redesigned to comply with the current presentation and information standard of Philips Semiconductors. • • Removed type number 74HCT73.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger 15. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification.
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74HC73 Philips Semiconductors Dual JK flip-flop with reset; negative-edge trigger 19. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information .
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