Datasheet

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 12 November 2004 10 of 21
Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
t
h
hold time nJ, nK to nCP see Figure 6
V
CC
= 2.0 V 3 −8- ns
V
CC
= 4.5 V 3 −3- ns
V
CC
= 6.0 V 3 −2- ns
f
max
maximum clock frequency see Figure 6
V
CC
= 2.0 V 6.0 23 - MHz
V
CC
= 4.5 V 30 70 - MHz
V
CC
= 6.0 V 35 83 - MHz
V
CC
= 5.0 V; C
L
= 15 pF - 77 - MHz
C
PD
power dissipation capacitance per
flip-flop
V
I
= GND to V
CC
[1]
-30-pF
T
amb
= −40 °C to +85 °C
t
PHL
, t
PLH
propagation delay nCP to nQ see Figure 6
V
CC
= 2.0 V - - 200 ns
V
CC
= 4.5 V - - 40 ns
V
CC
= 6.0 V - - 34 ns
propagation delay n
CP to nQ see Figure 6
V
CC
= 2.0 V - - 200 ns
V
CC
= 4.5 V - - 40 ns
V
CC
= 6.0 V - - 34 ns
propagation delay n
R to nQ, nQ see Figure 7
V
CC
= 2.0 V - - 180 ns
V
CC
= 4.5 V - - 36 ns
V
CC
= 6.0 V - - 31 ns
t
THL
, t
TLH
output transition time see Figure 6
V
CC
= 2.0 V - - 95 ns
V
CC
= 4.5 V - - 19 ns
V
CC
= 6.0 V - - 16 ns
t
W
nCP clock pulse width HIGH or LOW see Figure 6
V
CC
= 2.0 V 100 - - ns
V
CC
= 4.5 V 20 - - ns
V
CC
= 6.0 V 17 - - ns
n
R reset pulse width HIGH or LOW see Figure 7
V
CC
= 2.0 V 100 - - ns
V
CC
= 4.5 V 20 - - ns
V
CC
= 6.0 V 17 - - ns
t
rem
removal time nR to nCP see Figure 7
V
CC
= 2.0 V 100 - - ns
V
CC
= 4.5 V 20 - - ns
V
CC
= 6.0 V 17 - - ns
Table 8: Dynamic characteristics
…continued
GND = 0 V; t
r
=t
f
= 6 ns; C
L
= 50 pF; see Figure 8.
Symbol Parameter Conditions Min Typ Max Unit