Datasheet

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 12 November 2004 11 of 21
Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
t
su
set-up time nJ, nK to nCP see Figure 6
V
CC
= 2.0 V 100 - - ns
V
CC
= 4.5 V 20 - - ns
V
CC
= 6.0 V 17 - - ns
t
h
hold time nJ, nK to nCP see Figure 6
V
CC
= 2.0 V 3 - - ns
V
CC
= 4.5 V 3 - - ns
V
CC
= 6.0 V 3 - - ns
f
max
maximum clock frequency see Figure 6
V
CC
= 2.0 V 4.8 - - MHz
V
CC
= 4.5 V 24 - - MHz
V
CC
= 6.0 V 28 - - MHz
T
amb
= −40 °C to +125 °C
t
PHL
, t
PLH
propagation delay nCP to nQ see Figure 6
V
CC
= 2.0 V - - 240 ns
V
CC
= 4.5 V - - 48 ns
V
CC
= 6.0 V - - 41 ns
propagation delay n
CP to nQ see Figure 6
V
CC
= 2.0 V - - 240 ns
V
CC
= 4.5 V - - 48 ns
V
CC
= 6.0 V - - 41 ns
propagation delay n
R to nQ, nQ see Figure 7
V
CC
= 2.0 V - - 220 ns
V
CC
= 4.5 V - - 44 ns
V
CC
= 6.0 V - - 38 ns
t
THL
, t
TLH
output transition time see Figure 6
V
CC
= 2.0 V - - 110 ns
V
CC
= 4.5 V - - 22 ns
V
CC
= 6.0 V - - 19 ns
t
W
nCP clock pulse width HIGH or LOW see Figure 6
V
CC
= 2.0 V 120 - - ns
V
CC
= 4.5 V 24 - - ns
V
CC
= 6.0 V 20 - - ns
n
R reset pulse width HIGH or LOW see Figure 7
V
CC
= 2.0 V 120 - - ns
V
CC
= 4.5 V 24 - - ns
V
CC
= 6.0 V 20 - - ns
Table 8: Dynamic characteristics
…continued
GND = 0 V; t
r
=t
f
= 6 ns; C
L
= 50 pF; see Figure 8.
Symbol Parameter Conditions Min Typ Max Unit