Datasheet

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 12 November 2004 12 of 21
Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
[1] C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
=C
PD
× V
CC
2
× f
i
× N+∑(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑(C
L
× V
CC
2
× f
o
) = sum of outputs.
t
rem
removal time nR to nCP see Figure 7
V
CC
= 2.0 V 120 - - ns
V
CC
= 4.5 V 24 - - ns
V
CC
= 6.0 V 20 - - ns
t
su
set-up time nJ, nK to nCP see Figure 6
V
CC
= 2.0 V 120 - - ns
V
CC
= 4.5 V 24 - - ns
V
CC
= 6.0 V 20 - - ns
t
h
hold time nJ, nK to nCP see Figure 6
V
CC
= 2.0 V 3 - - ns
V
CC
= 4.5 V 3 - - ns
V
CC
= 6.0 V 3 - - ns
f
max
maximum clock frequency see Figure 6
V
CC
= 2.0 V 4.0 - - MHz
V
CC
= 4.5 V 20 - - MHz
V
CC
= 6.0 V 24 - - MHz
Table 8: Dynamic characteristics
…continued
GND = 0 V; t
r
=t
f
= 6 ns; C
L
= 50 pF; see Figure 8.
Symbol Parameter Conditions Min Typ Max Unit