Datasheet

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 12 November 2004 13 of 21
Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
12. Waveforms
The shaded areas indicate when the input is permitted to change for predictable output
performance.
V
M
= 0.5 × V
I
.
Fig 6. Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the
clock pulse width, the J and K to n
CP set-up and hold times, the output transition
times and the maximum clock frequency
V
M
= 0.5 × V
I
.
Fig 7. Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays
and the reset pulse width and the n
R to nCP removal time
t
su
1/f
max
t
h
nCP input
V
M
V
M
t
h
t
su
t
W
nJ, nK
input
001aab983
nQ output
nQ output
t
PHL
t
PLH
V
M
t
TLH
t
THL
t
TLH
V
M
t
THL
t
PLH
t
PHL
001aab984
nQ output
t
W
nR input
V
M
nQ input
nCP input
V
M
t
rem
t
PHL
t
PLH