Datasheet

9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 12 November 2004 2 of 21
Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
3. Quick reference data
[1] C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
=C
PD
× V
CC
2
× f
i
× N+∑(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑(C
L
× V
CC
2
× f
o
) = sum of outputs.
4. Ordering information
Table 1: Quick reference data
GND = 0 V; T
amb
=25 ° C; t
r
=t
f
= 6 ns.
Symbol Parameter Conditions Min Typ Max Unit
t
PHL
, t
PLH
propagation delay C
L
= 15 pF; V
CC
=5 V - -
n
CP to nQ - 16 - ns
n
CP to nQ - 16 - ns
n
R to nQ, nQ - 15 - ns
f
max
maximum clock
frequency
C
L
= 15 pF; V
CC
= 5 V - 77 - MHz
C
I
input capacitance - 3.5 - pF
C
PD
power dissipation
capacitance per flip-flop
V
I
= GND to V
CC
[1]
-30-pF
Table 2: Ordering information
Type number Package
Temperature range Name Description Version
74HC73N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HC73D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HC73DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; body width
5.3 mm
SOT337-1
74HC73PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body
width 4.4 mm
SOT402-1