Datasheet

ManualsBrandsNXP ManualsAnalogue SwitchesAnalogue Switch IC SOT-363

1. General description

The 74LVC1G3157 provides one analog multiplexer/demultiplexer with one digital select

input (S), two independent inputs/outputs (Y0, Y1) and a common input/output (Z).

Schmitt trigger action at the select input makes the circuit tolerant of slower input rise and

fall times across the entire V

range from 1.65 V to 5.5 V.

2. Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V

 Very low ON resistance:

 7.5  (typical) at V

=2.7V

 6.5  (typical) at V

=3.3V

 6  (typical) at V

=5V

 Switch current capability of 32 mA

 Break-before-make switching

 High noise immunity

 CMOS low power consumption

 TTL interface compatibility at 3.3 V

 Latch-up performance meets requirements of JESD 78 Class I

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 Control input accepts voltages up to 5.5 V

 Multiple package options

 Specified from 40 C to +85 C and from 40 C to +125 C

74LVC1G3157

2-channel analog multiplexer/demultiplexer

Rev. 5 — 6 December 2012 Product data sheet

Summary of content (25 pages)

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74LVC1G3157 2-channel analog multiplexer/demultiplexer Rev. 5 — 6 December 2012 Product data sheet 1. General description The 74LVC1G3157 provides one analog multiplexer/demultiplexer with one digital select input (S), two independent inputs/outputs (Y0, Y1) and a common input/output (Z). Schmitt trigger action at the select input makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 1.65 V to 5.5 V. 2. Features and benefits  Wide supply voltage range from 1.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G3157GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363 74LVC1G3157GV 40 C to +125 C SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457 74LVC1G3157GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1  1.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 6. Pinning information 6.1 Pinning 74LVC1G3157 74LVC1G3157 Y1 1 6 S GND 2 5 VCC Y0 3 4 Z Y1 1 6 S GND 2 5 VCC Y0 3 4 Z Pin configuration SOT363 and SOT457 Pin configuration SOT886 1 6 S GND 2 5 VCC Y0 3 4 Z Transparent top view 001aac357 Fig 4. Y1 001aaf546 Transparent top view 001aac356 Fig 3. 74LVC1G3157 Fig 5. Pin configuration SOT891, SOT1115 and SOT1202 6.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions [1] VI input voltage IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V ISK switch clamping current VI < 0.5 V or VI > VCC + 0.5 V [2] Min Max Unit 0.5 +6.5 V 0.5 +6.5 V 50 - mA - 50 mA 0.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter HIGH-level input voltage VIH 40 C to +85 C Conditions VCC = 1.65 V to 1.95 V LOW-level input voltage Min Max Min Unit Max 0.65VCC - - 0.65VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 3 V to 3.6 V 2.0 - - 2.0 - V 0.7VCC - - 0.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 10.1 Test circuits VCC VIL or VIH S Y0 1 Z Y1 2 switch switch S 1 VIH 2 VIL IS VI VO GND 001aac358 VI = VCC or GND and VO = GND or VCC. Fig 6. Test circuit for measuring OFF-state leakage current VCC VIL or VIH IS S Y0 1 Z Y1 2 switch S 1 VIH 2 VIL switch VI VO GND 001aac359 VI = VCC or GND and VO = open circuit. Fig 7. Test circuit for measuring ON-state leakage current 10.
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4LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer Table 8. ON resistance …continued At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 9 to Figure 14. Symbol RON(rail) Parameter ON resistance (rail) 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max ISW = 4 mA; VCC = 1.65 V to 1.95 V - 8.2 18 - 27  ISW = 8 mA; VCC = 2.3 V to 2.7 V - 7.1 16 - 24  ISW = 12 mA; VCC = 2.7 V - 6.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 10.3 ON resistance test circuit and graphs mna673 40 RON (Ω) 30 VSW V switch VCC VIL or VIH S Y0 1 Z Y1 2 (1) S 1 VIL 2 VIH 20 switch (2) (3) 10 (4) (5) VI ISW GND 0 0 1 2 3 4 5 VI (V) 001aac360 RON = VSW / ISW. (1) VCC = 1.8 V. (2) VCC = 2.5 V. (3) VCC = 2.7 V. (4) VCC = 3.3 V. (5) VCC = 5.0 V. Fig 8. Test circuit for measuring ON resistance 001aaa712 55 RON (Ω) Fig 9.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 001aaa709 13 001aaa710 10 RON (Ω) RON (Ω) 11 8 (1) (1) 9 (2) (2) 6 (3) (3) 7 (4) (4) 5 4 0 0.5 1.0 1.5 2.0 2.5 3.0 VI (V) 0 1 2 3 4 VI (V) (1) Tamb = 125 C. (1) Tamb = 125 C. (2) Tamb = 85 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (3) Tamb = 25 C. (4) Tamb = 40 C. (4) Tamb = 40 C. Fig 12. ON resistance as a function of input voltage; VCC = 2.7 V Fig 13.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 11. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18. Symbol Parameter propagation delay tpd enable time ten 40 C to +85 C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V - - 2 - 3.0 ns VCC = 2.3 V to 2.7 V - - 1.2 - 2.0 ns VCC = 2.7 V - - 1.0 - 1.5 ns VCC = 3 V to 3.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 11.1 Waveforms and test circuits VI Yn or Z input VM VM GND tPLH tPHL VOH Z or Yn output VM VM VOL 001aac361 Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 15.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 0.5VCC VCC VI G VO RL S Y0 Z Y1 CL GND 001aac367 a. Test circuit VI 0.5VI 0.9VO 0.9VO VO tb-m 001aag572 b. Input and output measurement points Fig 17. Test circuit for measuring break-before-make timing VEXT VCC VI RL VO G DUT RT CL RL mna616 Test data is given in Table 11. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer Table 11. Test data Supply voltage Input Load VEXT VCC VI tr, tf CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 1.65 V to 1.95 V VCC  2.0 ns 50 pF 500  open GND 2VCC 2.3 V to 2.7 V VCC  2.0 ns 50 pF 500  open GND 2VCC 2.7 V VCC  2.5 ns 50 pF 500  open GND 2VCC 3 V to 3.6 V VCC  2.5 ns 50 pF 500  open GND 2VCC 4.5 V to 5.5 V VCC  2.5 ns 50 pF 500  open GND 2VCC 11.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 11.3 Test circuits 0.5VCC VCC VIL or VIH 0.1 μF S Y0 1 Z Y1 2 S 1 VIL 2 VIH RL 10 μF switch D CL 600 Ω fi switch GND 001aac363 Fig 19. Test circuit for measuring total harmonic distortion 0.5VCC VCC VIL or VIH fi 0.1 μF S Y0 1 Z Y1 2 RL switch S 1 VIL 2 VIH switch dB CL 50 Ω GND 001aac364 Adjust fi voltage to obtain 0 dBm level at output.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer VCC S Y0 1 Z Y1 2 switch Rgen VI G VO RL CL Vgen GND 001aac366 a. Test circuit logic (S) off input on VO off ΔVO 001aac478 b. Input and output pulse definitions Qinj = VO  CL. VO = output voltage variation. Rgen = generator resistance. Vgen = generator voltage. Fig 22.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 12. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 c bp Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer Plastic surface-mounted package (TSOP6); 6 leads D SOT457 E B y A HE 6 5 X v M A 4 Q pin 1 index A A1 c 1 2 3 Lp bp e w M B detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A A1 bp c D E e HE Lp Q v w y 1.1 0.9 0.1 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer SOT886 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm b 1 2 3 4x (2) L L1 e 6 5 e1 4 e1 6x A (2) A1 D E terminal 1 index area 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit max nom min mm A(1) 0.5 A1 b D E 0.04 0.25 1.50 1.05 0.20 1.45 1.00 0.17 1.40 0.95 e e1 0.6 0.5 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Notes 1.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 4× (1) L L1 e 6 5 4 e1 e1 6× A (1) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 Note 1.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm 1 SOT1115 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit A(1) A1 b D E e e1 max 0.35 0.04 0.20 0.95 1.05 nom 0.15 0.90 1.00 0.55 min 0.12 0.85 0.95 mm 1 mm L L1 0.35 0.40 0.30 0.35 0.27 0.32 0.3 Note 1. Including plating thickness. 2.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm 1 SOT1202 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit 1 mm A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.05 1.05 0.35 0.40 nom 0.15 1.00 1.00 0.55 0.35 0.30 0.35 min 0.12 0.95 0.95 0.27 0.32 mm Note 1. Including plating thickness. 2.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 13. Abbreviations Table 13. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor TTL Transistor-Transistor Logic HBM Human Body Model ESD ElectroStatic Discharge MM Machine Model DUT Device Under Test 14. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC1G3157 v.5 20121206 Product data sheet - 74LVC1G3157 v.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.2 11.3 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . .