Datasheet

ManualsBrandsNXP ManualsDevelopment Boards & KitsDevelopment Board that Supports the QorIQ LS1046A Architecture Processor

Layerscape FRWY-LS1046A Board

Reference Manual

Supports FRWY-LS1046A Board Revision B

NXP Semiconductors

Document Number: FRWY-LS1046ARM

Reference Manual Rev. 0, 26 April 2019

Summary of content (46 pages)

PAGE 1
NXP Semiconductors Document Number: FRWY-LS1046ARM Reference Manual Layerscape FRWY-LS1046A Board Reference Manual Supports FRWY-LS1046A Board Revision B Rev.
PAGE 2
Contents Contents Chapter 1 FRWY-LS1046A Overview..................................................................3 1.1 Acronyms and abbreviations.........................................................................................................................................3 1.2 Related documentation.................................................................................................................................................4 1.3 Block diagram....................................
PAGE 3
Acronyms and abbreviations Chapter 1 FRWY-LS1046A Overview ® The Layerscape LS1046A Freeway (FRWY-LS1046A) board is a high-performance development platform that supports the ® ® QorIQ LS1046A architecture processor capable of supporting more than 32000 CoreMark performance. The FRWY-LS1046A board supports the QorIQ LS1046A processor, onboard DDR4 memories, multiple Gigabit Ethernet ports, USB 3.0 ports, M.2 ™ Key-E slots for Wi-Fi, and expansion board options via a mikroBUS socket.
PAGE 4
FRWY-LS1046A Overview Table 1.
PAGE 5
Block diagram Table 2. Related documentation (continued) Document Description Link / how to access QorIQ LS1046A Data Sheet Provides information about LS1046A electrical characteristics, hardware design considerations, and ordering information QorIQ LS1046A Reference Manual LS1046A.pdf Provides a detailed description about the QorIQ LS1046A LS1046ARM.
PAGE 6
FRWY-LS1046A Overview Figure 1. FRWY-LS1046A block diagram 1.4 Board features The table below describes the features of the FRWY-LS1046A. Layerscape FRWY-LS1046A Board Reference Manual, Rev.
PAGE 7
Board features Table 3. FRWY-LS1046A features Board feature Processor feature used Processor Description QorIQ LS1046A processor NOTE For details on the LS1046A processor, see QorIQ LS1046A Reference Manual.
PAGE 8
FRWY-LS1046A Overview Table 3.
PAGE 9
Board features Table 3. FRWY-LS1046A features (continued) Board feature Power supply Processor feature used Description • 12 V input power from DC input adapter • 1/0.9 V for core VDD, USB_SVDD, USB_SDVDD, and SVDD • 1.2 V for DDR4 G1VDD • 0.6 V for DDR4 VTT/VREF • 2.5 V for DDR4 VPP • 3.3 V for DVDD • 3.3 V for EVDD • 3.3 V for USB_HVDD • 1.8 V for OVDD and LVDD • 1.35 V for XVDD • 2.5 V for TVDD • 1.8 V / GND for TA_PROG_SFP (GPIO-controlled) • 1/0.9 V for TA_BB_VDD • 2.
PAGE 10
FRWY-LS1046A Overview Table 3. FRWY-LS1046A features (continued) Board feature Processor feature used Description Debug • Supports Arm Cortex 10-pin JTAG connector • Supports micro-USB port to access serial port as console for debug GPIO • Supports a 2x10 GPIO header (1.8 V) • Supports bi-directional (configurable) inputs/outputs 1.5 Board top/bottom views The figure below shows the top-side view of the FRWY-LS1046A. Figure 2.
PAGE 11
Board top/bottom views Figure 3. FRWY-LS1046A bottom view Layerscape FRWY-LS1046A Board Reference Manual, Rev.
PAGE 12
FRWY-LS1046A Functional Description Chapter 2 FRWY-LS1046A Functional Description This chapter describes the features and functions of the FRWY-LS1046A. For details of the LS1046A processor features, see QorIQ LS1046A Reference Manual.
PAGE 13
Power supplies Synchronous step-down regulator 5V0 5V@2A USB 3.0 Ports x2 L T8609SEV#PB F AC 110/220V@ 50/60Hz 12V_PS P ower adapter GST60A12-P1J 12V-5A (60W ) DC power adapter 12V_IN Step-down regulator 12V0 1/0.9V@20A GND_IN PJ 063AH V/A/P PL T10HH401100PNB INA220A CPU_VDD 1mOHm/3W L TC7150SEY#PB F 3V3 3.3V@10A L DO Regulator VDD_EN (LX1) 1V@1A (LX2) 1.8V@2A (LX3) 1.35V@0.4A (LX5) 1.2V@3A (LX6) 0.6V@1A (LX7) 2.
PAGE 14
FRWY-LS1046A Functional Description The table below shows the details of the power jack on the board to connect external 12 V power adapter. Table 5. Power jack Part identifier Part number Description J1 PJ-063AH Plug/mating plug specifications: • Inside diameter: 2.1 mm • Outside diameter: 5.5 mm • Rating: 8 A 2.1.2 Secondary power supplies The table below describes the FRWY-LS1046A power supply devices that generate secondary power supplies for the board. Table 6.
PAGE 15
Power supplies Table 6. FRWY-LS1046A power supply devices (continued) Reference designator Device Power supply voltage U560 LT8642SEV (Linear Technology) 3V3 (3.3 V at 10 A) Description • Supply for processor DVDD and EVDD • Filtered 3V3 power for USB (USB_HVDD) power supply of the LS1046A processor • Supply for the following board components: — Si5332FD10253-GM2 clock generator — M.
PAGE 16
FRWY-LS1046A Functional Description Table 6. FRWY-LS1046A power supply devices (continued) Reference designator Device Power supply voltage Description SW5LX: GVDD (1.2 V 3 A) • Supply for DDR controller input/output (GVDD) SW6LX: DDR_VTT (0.6 V at 1 A) Supply for DDR address and control bus termination (VTT) • Supply for DDR4 SDRAM memory chips NOTE VTT_Mode is enabled (sink current is up to 700 mA (typical)). SW7LX: 2V5 (2.
PAGE 17
Power supplies From DC jack 12V VIN 31.4ms soft-start from 12V 3.3V LT8642SEV 3V3 3.87ms 5V LT8609SEV 3V3 PG soft-start from 3.3V P G tvin_rise+tstest_done+ tfirst+S oft_start 1.5ms+1.4ms+0.1ms+4ms=7ms 2.5V PF8100 SW7 1.8V P F8100 S EQ8 internally programmed 2.5V,OVDD, XVDD P ower Tier1 P F8100 S EQ8 internally programmed PF8100 SW2 P F8100 S EQ8 internally programmed 1.35V PF8100 SW3 5ms 1.0V, LDO[1:4] P F8100 S EQ18 internally programmed PF8100 S W1, LDO[1:4] 2ms tss VDD (0.
PAGE 18
FRWY-LS1046A Functional Description Table 7. VDD current/power measurement Measurement device Shunt resistor value Notes INA220AIDGST 0.001 The VDD supply powers the LS1046A core (1/0.9 V), USB (USB_SDVDD and USB_SVDD), and SerDes (SVDD) power supplies 2.2 Clocks The FRWY-LS1046A has a clock generator (Si5332FD10253-GM2), which generates most of the clocks required for the functioning of the LS1046A processor and different board peripherals.
PAGE 19
DDR interface Table 8. FRWY-LS1046A clocks Clock generator Clocks Specifications U50: Si5332FD10253-GM2 OUT0: • Frequency: 125 MHz QSGPHY_REFCLK_125M_[P,N] • Output type: LVDS Destination QSGMII PHY • Operating voltage: 3.3 V OUT1: • Frequency: 100 MHz DIFF_SYSCLK_[P, N] • Output type: LVDS DIFF_SYSCLK • Operating voltage: 3.3 V OUT2: • Frequency: 100 MHz SD1_REFCLK2_[P, N] • Output type: HCSL SerDes1 controller (PLL 2) • Operating voltage: 3.3 V U523: PCF2129AT M.
PAGE 20
FRWY-LS1046A Functional Description VREFCA 0V6 GVDD 1V2 LS 1046A VPP VDD 2V5 1V2 DQ[48:63] DQ[32:47] DQ[16:31] DQ[15:0] ECC[7:0] D1_MECC[7:0] D1_ MDQ[63:0] D1_MDQS[7:0],8 D1_MDM[7:0],8 DDR4 SDRAM MT40A512M16JY-083E:B D1_MB A[1:0] 8Gb 512Mbit x16 discreet chip (5 nos) + ECC D1_MA[13:0] D1_MCS[1:0] D1_MCK[1:0] /MODT[1:0] D1_MCKE [1:0] D1_MRAS /MCAS /MWE /MACT D1_MAPAR /MB G[1:0] D1_MALERT G1VDD 162E 162E 3V3 GVDD T E R M I N A T I O N 1.0K D1_MDIC1 } VTT 0.
PAGE 21
SerDes interface • 1.2 V and 2.5 V (VPP) for DDR4 SDRAM memory chips • 0.6 V (VTT) for DDR address and control bus termination For more information on board power supplies, see Secondary power supplies on page 14. 2.4 SerDes interface The FRWY-LS1046A supports serializer/deserializer (SerDes) connections on three of the eight lanes of SerDes1 and SerDes2 modules of the LS1046A processor. The figure below shows the SerDes diagram of the FRWY-LS1046A.
PAGE 22
FRWY-LS1046A Functional Description Figure 10. SerDes1 protocol combinations The figure below shows the possible SerDes2 protocol combinations that can be used on the FRWY-LS1046A. Figure 11. SerDes2 protocol combinations 2.4.1 Ethernet interface The onboard Ethernet PHY, NXP F104S8A PHY (U123), connects to the TSN switch of the LS1046A processor using QSGMII protocol over SerDes1 lane 2/B. The figure below shows the FRWY-LS1046A Ethernet diagram. Layerscape FRWY-LS1046A Board Reference Manual, Rev.
PAGE 23
SerDes interface NXP F 104S 8A 138-P IN QFN L S1046A PHY 0.1µF || RX SerDes1 (lane 2/B) SD1_RX2_P/N 0.1µF || TX RDP /N S D1_TX2_P/N 2V5 TDP /N 2V5 EMI2 _MDC EMI2_MDIO LE D[0:1]_P HY0 P OR T1 P0_D0P/N P0_D1P/N P0_D2P/N P0_D3P/N P1_D0P/N P1_D1P/N P1_D2P/N P1_D3P/N RJ -45 with Transformer MDC MDIO GPIO3_27 4.7K P OR E S E T_B OVDD 74AUP1G09GW MDINT Clock generator OUT0 Si5332FD10253-GM2 [Silicon Labs] OUT0 (LVDS 33) 0.
PAGE 24
FRWY-LS1046A Functional Description Table 10. Hardware bootstrap settings for QSGMII PHY Feature Settings PHY address PHYADD[4:2] = 0x1C - 0x1F REFCLK selection REFCLK_SEL[1:0] = 00: 125 MHz clock is used as REFCLK COMA_MODE COMA_MODE = 0: PHY comes out of reset as soon as reset is de-asserted 2.4.2 M.2 PCIe slots The FRWY-LS1046A supports two M.2 Key-E slots (J46 and J52), which are supported through SerDes2 lane 1 and lane 3, respectively.
PAGE 25
USB interface USB 3.0 Stacked 1x2 VE RTICAL R IGHT-ANGLE LS1046A USB 1_D_[P ,M] 90W diff. imp. USB 1_TX_[P ,M] USB 1_R X_[P ,M] USB 1_VB US USB 1 74LVC1G04GW USB 1_PW R FAULT <=2A 5V0 USB 1_DR VVB US 200 USB 1_R ESR E F USB 1_ID Host Mode USB 1_5V NX5P 3090UK GSB 311 231HR 49.9 USB 2_DP,DM USB 3.0 type A 90W diff. imp. USB 2_TXP ,TXM USB 2_R XP ,R XM USB 2 USB 2_VB US 200 USB 2_R ESR E F USB 2_ID Host Mode 49.
PAGE 26
FRWY-LS1046A Functional Description The USB2_DRVVBUS and USB2_PWRFAULT signals are muxed with I2C3_SCL and I2C3_SDA signals, respectively. A multiplexer NX3DV42GU (from NXP) is used to demux the muxed signals.
PAGE 27
SDHC interface Table 12. QSPI NOR flash memory Part identifier Part number Description U532 MT25QU512ABB8ESF-0SIT • Type: Serial NOR flash memory • Density: 512 Mbit (64 MB) • Operating voltage: 1.8 V 2.6.2 NAND flash memory The table below describes the NAND flash memory used in FRWY-LS1046A. Table 13.
PAGE 28
FRWY-LS1046A Functional Description NOTE The micro-SD card available with the board does not support ultra high-speed (UHS) modes. The part number of the micro-SDHC connector J55 is 95220030-14RRF. The table below shows the pinout details of the microSDHC connector. Table 14. Micro-SDHC connector pinout Pin number SDHC signals Direction with respect to LS1046A I/O voltage 1 SD_DATA2 Bidirectional 3.
PAGE 29
UART interface Pinout LS1046A 3V3 UART_S OUT UART_S IN GND UART1_SIN UART1_SIN UART1_SOUT Jumper *when using USB for console otherwise open HDR 1x2 Console port USB-to-UART bridge UART1_S OUT CP2102N-A01-GQFN20 [Silicon Labs] MikroBUS socket DVDD (3.3V) micro USB UART3_SIN UART3_SOUT Pinout UART2_S IN UART2_SOUT UART2_CTS _B UART2_RTS _B UART2_SIN UART2_SOUT UART2_CTS _B /UART4_SIN UART2_RTS _B /UART4_SOUT GND UART_R TS 3V3 UART_S IN UART_S OUT UART_CTS UART expansion header Figure 17.
PAGE 30
FRWY-LS1046A Functional Description Table 15. UART expansion header J73 pinout (continued) Pin number UART signals Direction with respect to LS1046A 2 UART1_SOUT From LS1046A 3 UART1_SIN To LS1046A 4 GND I/O voltage The table below shows pinout details of UART expansion header J60. Table 16.
PAGE 31
MikroBUS socket NOTE The LS1046A SPI signals are on 1.8 V (OVDD) and they are converted to 3.3 V level using level translators. The table below describes chip select mapping for FRWY-LS1046A SPI interface. Table 17. SPI chip select mapping Chip select Connected device SPI_PCS0 MikroBUS socket SPI_PCS1 Expansion header SPI_PCS2 Expansion header SPI_PCS3 Expansion header The table below shows pinout details of SPI expansion header J66. Table 18.
PAGE 32
FRWY-LS1046A Functional Description Figure 19. MikroBUS pin specifications The FRWY-LS1046A mikroBUS socket supports different types of add-on boards, called click boards, which can be accessed through SPI, UART3, PWM, or I2C interface.
PAGE 33
I2C interface Click boards are plug and play solutions to add new functionality to the board design. A click board has two columns each of eight pins, which connect to the two 1x8 headers of a mikroBUS socket. The table below lists some of the click boards that can be added on the FRWY-LS1046A mikroBUS socket. Table 19. Supported click boards Part number Name Supported communicatio n interface Operating voltage Description MIKROE-1597 BLE P click SPI 3.3 V Contains a Bluetooth low energy chip.
PAGE 34
FRWY-LS1046A Functional Description 3V3 I2C1 DVDD (3.3V) B uffer LS1046A PCA9510ADP 3V3 3V3 3V3 I2C1_S DA I2C1_S CL I2C2 SDHC_CD_B SDHC_W P USB 2_PW R FAULT / I2C3_SDA USB 2_DR VVB US / I2C3_SCL 1 0 I2C3_USB 2_SE L GPIO3_23 0 I2C1_CH0 1 I2C1_M2CARD1 2 I2C1_M2CARD2 3 I2C1_uB US PCA9546APW Addr = 0x77 3V3 I2C3 3.3V PCIe M.2 Key-E "1" PCIe M.
PAGE 35
JTAG header Table 20. I2C bus device map (continued) I2C bus 7-bit address Device Description Notes 0x4C SA56004ED Temperature sensor (U28) Monitors processor thermal diode 0x51 PCF2129AT Battery-backed clock (U523) Provides time and date functionality with battery backup option 0x52 and 0x53 CAT24C04WI-G System ID EEPROM (U524) Stores board-specific data, such as MAC addresses and serial number / errata I2C1_CH 1 I2C address is PCIe M.
PAGE 36
FRWY-LS1046A Functional Description LS1046A Arm JTAG header OVDD 4.7K CPU_TMS TMS TCK CPU_TCK CPU_TDO TDO TDI OVDD (1.8V) CPU_TDI OVDD 2 1 4 3 6 5 8 7 10 9 OVDD 10K FTSH-105-01-L-DV-K 10K TBSCAN_EN_B CPU_J TAG_R ST_B Reset control Figure 22. JTAG diagram The table below describes the JTAG header. Table 22.
PAGE 37
GPIOs Table 23.
PAGE 38
FRWY-LS1046A Functional Description Table 23.
PAGE 39
Interrupt handling 2.14 Interrupt handling Apart from handling interrupts from interrupt sources within the processor, the generic interrupt controller (GIC) of the LS1046A processor can handle interrupts from external interrupt sources. In the FRWY-LS1046A, the onboard interrupt sources are connected to interrupt controller through IRQ01, IRQ03-IRQ07 pins of the processor for interrupt controller to handle their interrupt signals.
PAGE 40
FRWY-LS1046A Functional Description TD1_ANODE and TD1_CATHODE signals) to the temperature sensor. Upon detecting thermal problems, the temperature sensor sends alarm signals (through THERM_WARN_B and THERM_FAULT_B interrupt signals) to the processor. These interrupts can be used to power down the system to protect the processor from over-temperature damage. The figure below shows thermal management in the FRWY-LS1046A.
PAGE 41
LEDs Table 26. SW1 settings Switch Supported function Settings SW1[1:9] RCW fetch location • 0_0100_0100: QSPI NOR flash (default setting) CFG_RCW_SRC[0:8] • 0_0100_0000: Micro-SD card • 1_0000_01xx: NAND flash (8-bit bus, 2 KB page, 64 pages/block) (LS1043A only)1 • 0_1001_1110: Hard-coded RCW SW1[10] System clock source CFG_ENG_USE0 • 0: DIFF_SYSCLK/DIFF_SYSCLK_B (differential clock) - 100 MHz (fixed) (default setting) • 1: SYSCLK (single-ended clock) - 100 MHz (fixed) 1.
PAGE 42
FRWY-LS1046A Functional Description Table 27. FRWY-LS1046A LEDs (continued) Reference designator LED color LED name Description (when LED is ON) D509 Green 4_GRN_LED Four stacked LEDs to indicate: • Power status • System readyness • PROG_SFP fuse programming power enable 1. It is placed on the bottom side of PCB next to J46 connector. 2.18 System reset The figure below shows the reset diagram for the FRWY-LS1046A.
PAGE 43
System reset Table 28. Reset sources Reset source Reset reason Actions taken Power ON / power failure Initialization after a power cycle All the onboard devices are reset after a power cycle. PLL and clock circuitry initialize to default configuration. SW6 Reset switch is pressed All devices are reset RESET_REQ_B1 Reset request from processor All devices are reset CPU JTAG header (J15) Reset JTAG debugger PORESET is asserted to the processor 1.
PAGE 44
Revision History Appendix A Revision History The table below summarizes the revisions to this document. Table 29. Revision history Revision Date Rev. 0 04/2019 Topic cross-reference Change description Initial public release Layerscape FRWY-LS1046A Board Reference Manual, Rev.
PAGE 45
PAGE 46
How To Reach Us Home Page: nxp.com Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. Web Support: NXP makes no warranty, representation, or guarantee regarding the suitability of its products for nxp.