Datasheet

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Table 7. VDD current/power measurement

Measurement device Shunt resistor value Notes

INA220AIDGST 0.001 The VDD supply powers the LS1046A core (1/0.9 V), USB

(USB_SDVDD and USB_SVDD), and SerDes (SVDD) power

supplies

2.2 Clocks

The FRWY-LS1046A has a clock generator (Si5332FD10253-GM2), which generates most of the clocks required for the

functioning of the LS1046A processor and different board peripherals. The figure below shows the clock diagram of the FRWY-

LS1046A.

LS1046A

DIFF_S YSCLK_P/N

SYS CL K

100 MHz (LVDS 33)

100 MHz HCS L

Internal Termination

REFCL K_P0

SD1_R EFCLK2_P/N

Differential

Single-ended

M2_1_R EF CLK_EN_B

CLKRE Q0

VDD_DIG/VDD_XTAL/VDDA

3V3

100 MHz LVCMOS (in-phas e) 1.8 V

F104S8A

(QS GMII P HY)

125 MHz LVDS

VDDO[0:4]

VDDO[5]

3V3

OVDD

S i5332FD10253-GM2

Silicon Labs

Internal Crystal

No External Crystal/OS C required

OUT0

OUT1

100 MHz HCS L 3.3 V 50 Ohms -Internal Termination

OUT2

SD2_RE FCLK2_P/N

100 MHz HCS L 3.3 V 50 Ohms -Internal Termination

SD2_REFCLK1_P/N

100 MHz HCS L 3.3 V 50 Ohms -

Internal Termination

DDRCLK

OUT7

OUT7B

100 MHz LVCMOS (in-phase) 1.8 V

OUT6

SerDes2

OUT4

OUT3

100 MHz HCS L

Internal Termination

REFCL K_P0

M2_2_R EFCLK_EN_B

CLKRE Q0

INPUT2

INPUT3

7-B it Ad dres s = 0x6A

OUT5

M.2 Key-E slot 1

M.2 Key-E slot 2

Figure 7. FRWY-LS1046A clock diagram

Si5332FD10253-GM2 uses an internal 50 MHz crystal oscillator to generate different frequencies.

NOTE

The table below provides details of different clocks of the FRWY-LS1046A.

FRWY-LS1046A Functional Description

Layerscape FRWY-LS1046A Board Reference Manual, Rev. 0, 26 April 2019

NXP Semiconductors