Datasheet

Table 8. FRWY-LS1046A clocks
Clock generator Clocks Specifications Destination
U50: Si5332FD10253-GM2
OUT0:
QSGPHY_REFCLK_125M_[P,N]
• Frequency: 125 MHz
• Output type: LVDS
• Operating voltage: 3.3 V
QSGMII PHY
OUT1:
DIFF_SYSCLK_[P, N]
• Frequency: 100 MHz
• Output type: LVDS
• Operating voltage: 3.3 V
DIFF_SYSCLK
OUT2:
SD1_REFCLK2_[P, N]
• Frequency: 100 MHz
• Output type: HCSL
• Operating voltage: 3.3 V
SerDes1 controller
(PLL 2)
OUT3,5
1
:
M2_1_REFCLK_[P,N]
M2_2_REFCLK_[P,N]
• Frequency: 100 MHz
• Output type: HCSL
• Operating voltage: 3.3 V
M.2 PCIe x1 slot 1
and slot 2
OUT4,6:
SD2_REFCLK2_[P, N]
SD2_REFCLK1_[P, N]
• Frequency: 100 MHz
• Output type: HCSL
• Operating voltage: 3.3 V
SerDes2 controller
(PLL 2 and PLL 1)
OUT7:
SYS_CLK_100MHz_LVCMOS
DDR_CLK_100MHz_LVCMOS
• Frequency: 100 MHz
• Output type: LVCMOS
• Operating voltage: 1.8 V
SYSCLK
DDRCLK
U523: PCF2129AT CLK_32KHZ
• Frequency: 32.768 kHz
• Operating voltage: 3.3 V
LS1046A RTC
1. The clock generator also controls the enable/disable for 100 MHz clocks to M.2 PCIe x1 slots. When the clock generator
detects a card in any of the M.2 slots, it enables clocks to the slots. Clocks are enabled for both slots even if only one slot is
populated with a card.
2.3 DDR interface
The FRWY-LS1046A has five onboard x16 DDR4 SDRAM memory chips with four chips supporting data transfer and one chip
supporting ECC. The figure below shows the DDR diagram of the FRWY-LS1046A.
DDR interface
Layerscape FRWY-LS1046A Board Reference Manual, Rev. 0, 26 April 2019
NXP Semiconductors
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