Datasheet

1V2
}
VTT
0.6V
D1_MDQS [7:0],8
D1
_
MDQ[63:0]
D1_MDM[7:0],8
D1_MRAS / MCAS / MWE / MACT
D1_MA[13:0]
D1_MBA[1:0]
3V3
PC33PF8100EAE S
D1_MAPAR / MB G[1:0]
D1_MDIC1
D1_MDIC0
162E
G1VDD
I2C1_CH0
Addr.= 0x52/0x53
D1_MCK[1:0] / MODT[1:0]
D1_MCS[1:0]
162E
LS1046A
RST_MEM_B
CPU_HR ESE T_B
VREFCA
0V6
DDR4 SDRAM
MT40A512M16JY-083E:B
8Gb 512Mbit x16
discreet chip (5 nos)
+ ECC
SPD
EEPROM
(optional)
D1_MCKE [1:0]
DQ[15:0]
DQ[16:31]
DQ[32:47]
DQ[48:63]
ECC[7:0]
D1_MECC[7:0]
T
E
R
M
I
N
A
T
I
O
N
VDD
1V2
VPP
2V5
GVDD
1V2
Fly-by
Topology
GVDD
3V3
0V6 DDR _VTT
D1_MALERT
1.0K
1V2
3V3
GVDD
source/sink
74AUP 1G07GW
SW 5
SW 6
VTT
Figure 8. DDR diagram
The part number of the SDRAM memory chips is MT40A512M16JY-083E:B (from Micron Technology). Following are the
characteristics of the FRWY-LS1046A DDR interface:
• Supports data rates of up to 2133 MT/s
• Supports 64-bit data bus
• Supports x16 discrete memory modules (eight data byte lanes + ECC)
• Supports double-bit error detection and single-bit error correction ECC (8- bit check word across 64-bit data)
• Supports single chip select (D1_MCS0_B)
The address and control signals to the DDR4 SDRAM memory chips are routed as per Fly-by topology and are terminated at VTT
(0.6 V). The data bus and associated signals, such as MDM and MDQS have one-to-one connections with individual x16 DDR4
memories. The ECC nibble goes to the fifth DDR4 memory.
The different components of the FRWY-LS1046A DDR interface are powered by the following power supplies generated by the
PF8100 power management integrated circuit (PMIC):
• 1.2 V (GVDD) for DDR controller input/output
FRWY-LS1046A Functional Description
Layerscape FRWY-LS1046A Board Reference Manual, Rev. 0, 26 April 2019
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NXP Semiconductors