Datasheet

• 1.2 V and 2.5 V (VPP) for DDR4 SDRAM memory chips
• 0.6 V (VTT) for DDR address and control bus termination
For more information on board power supplies, see Secondary power supplies on page 14.
2.4 SerDes interface
The FRWY-LS1046A supports serializer/deserializer (SerDes) connections on three of the eight lanes of SerDes1 and SerDes2
modules of the LS1046A processor. The figure below shows the SerDes diagram of the FRWY-LS1046A.
LS1046A
Lane 1/B
Lane 2/B
Lane 0, 1 & 3
4 Ports
QSGMII
NXP
F104S8A
QS G MII P HY
Lane 0 & 2
R J 45
E THE RNE T
1G/100M
Unused
P CIe M.2
Key-E
(W iFi)
PCIe x1
Lane 3/D
P CIe M.2
Key-E
(W iFi)
PCIe x1
Unused
SerDes1
SerDes2
Figure 9. SerDes diagram
The table below describes the FRWY-LS1046A SerDes assignments.
Table 9. SerDes assignments
SerDes
module
Lane Connectivity Port
SerDes1 Lane 2 NXP F104S8A 1.25 GbE quad-
port QSGMII PHY
Two 1.25 GbE 1x2 RJ45 ports on QSGMII MAC
interface
SerDes2 Lane 1 PCIe (Gen 1/2/3) PCIe x1 M.2 Key-E slot for 1630/2230 Wi-Fi module
Lane 3 PCIe (Gen 1/2/3) PCIe x1 M.2 Key-E slot for 1630/2230 Wi-Fi module
The figure below shows the possible SerDes1 protocol combinations that can be used on the FRWY-LS1046A.
SerDes interface
Layerscape FRWY-LS1046A Board Reference Manual, Rev. 0, 26 April 2019
NXP Semiconductors
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