Datasheet

MDIO
MDC
L S1046A
1V0_F104
P0_D0P /N
P0_D1P /N
P0_D3P /N
P0_D2P /N
VDDA
VDD
2V5
2V5
PHY
NXP F104S 8A
138-P IN QFN
EMI2_MDIO
EMI2_MDC
||
||
SerDes1
RX
(lane 2/B)
TX
2V5
VDD25
VDDA25
SD1_TX2_P /N
SD1_R X2_P /N
P1_D0P/N
P1_D1P /N
P1_D3P /N
P1_D2P /N
0.1µF
0.1µF
||
0.1µF
Clock generator
Si5332FD10253-GM2
[Silicon Labs]
OUT0
OVDD
QS G PHY1_R S T_B
2V5
MDINT
NRE SET
4.7K
IRQ01
4.7K
74AUP1G09GW
(A ND gate w ith open -drai n)
OVDD
4.7K
GPIO3_27
S W _QS G PHY1_R ST_ B
POR E S ET_B
OVDD
RE FCL K_P/N
OUT0 (LVDS 33)
125MHz
P HY ADDR = 0x1C -0x1F
RJ -45 with
Transformer
RJ -45 with
Transformer
LE D[0:1]_PHY0
LE D[0:1]_PHY1
1000BAS E LINK
ACT
1000B AS E LINK
ACT
RJ -45 with
Transformer
RJ -45 with
Transformer
LE D[0:1]_PHY2
LE D[0:1]_PHY3
1000B AS E L INK
ACT
1000B AS E L INK
ACT
P2_D0P /N
P2_D1P /N
P2_D3P /N
P2_D2P/N
P3_D0P /N
P3_D1P /N
P3_D3P /N
P3_D2P/N
PORT2
PORT1
PORT3
PORT4
TDP /N
RDP /N
Figure 12. Ethernet diagram
The EMI2 MDIO/MDC signals control the QSGMII PHY transceiver. EMI2 operates at TVDD (2.5 V) levels. The figure below
shows the EMI connections.
LS1046A
EMI1_MDIO
EMI1_MDC
LVDD
(1V8)
EMI2_MDIO
EMI2_MDC
2V5 2V5
MDIO
MDC
TVDD
(2V5)
NXP
F104S 8A
QS G MII P HY
ADDR = 1C..1F
Unused
Figure 13. EMI connections
The table below shows the hardware bootstrap settings required for the QSGMII PHY. These configuration settings are controlled
through onboard resistors.
SerDes interface
Layerscape FRWY-LS1046A Board Reference Manual, Rev. 0, 26 April 2019
NXP Semiconductors
23