Datasheet

Table 10. Hardware bootstrap settings for QSGMII PHY

Feature Settings

PHY address PHYADD[4:2] = 0x1C - 0x1F

REFCLK selection REFCLK_SEL[1:0] = 00: 125 MHz clock is used as REFCLK

COMA_MODE COMA_MODE = 0: PHY comes out of reset as soon as reset

is de-asserted

2.4.2 M.2 PCIe slots

The FRWY-LS1046A supports two M.2 Key-E slots (J46 and J52), which are supported through SerDes2 lane 1 and lane 3,

respectively. These connectors support only 1630 and 2230 PCIe Gen 1/2/3 card types to provide wireless connectivity, including

Wi-Fi and NFC. Note that:

• M.2 connectors have PCIe x1 (upto Gen 3) connectivity through the LS1046A processor

• M.2 connectors do not have UART, SDIO, or USB 2.0 connectivity through the LS1046A processor. Therefore, it could be

possible that some of the features related to these interfaces would not work in plugged-in M.2 modules.

• M.2 connectors have test points for coexistence signals. Because coexistence signal assignments on M.2 connectors is

vendor dependent, refer to vendor-specific documentation of M.2 modules for details.

2.4.2.1 Adapters for M.2 PCIe slots

You can use an adapter to convert an M.2 PCIe slot to a slot that supports PCIe Gen 1 and Gen 2 compliant endpoints. See links

below for more detail on such adapters:

• P11S-P11F - Duo PCI-E to M.2 (NGFF) Extender Board

• P11S-P11F - M.2 (NGFF) to PCI-E Extender Board

2.5

USB interface

The FRWY-LS1046A supports universal serial bus (USB) 3.0 connections with USB1 and USB2 controllers of the LS1046A

processor through a dual-port USB Type A connector. The figure below shows the USB diagram of the FRWY-LS1046A.

FRWY-LS1046A Functional Description

Layerscape FRWY-LS1046A Board Reference Manual, Rev. 0, 26 April 2019

NXP Semiconductors