Datasheet

Table 15. UART expansion header J73 pinout (continued)
Pin number UART signals Direction with respect to LS1046A I/O voltage
2 UART1_SOUT From LS1046A
3 UART1_SIN To LS1046A
4 GND
The table below shows pinout details of UART expansion header J60.
Table 16. UART expansion header J60 pinout
Pin number UART signals Direction with respect to LS1046A I/O voltage
1 GND 3.3 V
2 UART2_RTS_B/UART4_SOUT From LS1046A
3 3V3
4 UART2_SIN To LS1046A
5 UART2_SOUT From LS1046A
6 UART2_CTS_B/UART4_SIN To LS1046A
2.9 Serial peripheral interface
The FRWY-LS1046A supports serial peripheral interface (SPI) connections to the LS1046A processor through a mikroBUS socket
and SPI expansion header. The figure below shows the SPI diagram of the FRWY-LS1046A.
LS1046A
SPI_S OUT
SPI_S IN
SPI_SCK
OVDD
(1.8V)
Level
Translator
s
1.8V>3.3V
uBUS1_SPI_MISO
uBUS1_SPI_MOS I
uBUS1_SPI_CLK
uBUS1_S PI_CS0_B
74LVC2T45DC
SPI_PCS0
SPI_PCS1
SPI_PCS2
SPI_PCS3
Level
Translator
s
1.8V>3.3V
Level
Translator
s
1.8V>3.3V
Level
Translator
s
1.8V>3.3V
Level
translators
1.8V>3.3V
MikroBUS socket
CONN_SPI_MISO
CONN_SPI_MOSI
CONN_SPI_CLK
CONN_SPI_CS1_B
CONN_SPI_CS2_B
CONN_SPI_CS3_B
3V3
3V3
MOS I
MIS O
CLK
GND
CS1
CS2
CS3
Pinout
SPI expansion header
Figure 18. SPI diagram
FRWY-LS1046A Functional Description
Layerscape FRWY-LS1046A Board Reference Manual, Rev. 0, 26 April 2019
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NXP Semiconductors