Datasheet

LS1046A
I2C2
I2C1
I2C1_S DA
Addr = 0x77
PCA9546APW
3V3
I2C1_CH0
0
1
2
3
3V3
DVDD (3.3V)
SDHC_CD_B
SDHC_W P
I2C1_M2CARD1
I2C1_M2CARD2
I2C1_uB US
3.3V
3V3
PCA9510ADP
I2C1_S CL
I2C1_CH0
DDR1 uDIMM2
DDR1
SP D/NXID
Addr
0x52
3V3
VDD
Current
INA220A
3V3
Addr
0x40
I2C CHANNEL
From P CA9546APW
I2C3
I2C4
USB 2_PW R FAUL T / I2C3_SDA
USB 2_DR VVB US / I2C3_SCL
3V3
B uffer
MikroClick Module
PCIe M.2 Key-E
PCIe M.2 Key-E "2"
VB AT
Thermal
Moni tor
SA56004E D
3V3
THER M_ALARM_B
Addr
0x4C
THER M_W ARN_B
RTC
PCF2129AT
3V3
Addr
0x51
NXP PMIC
PF 8100
Addr
0x08
3V3
I2C4
3V3
NX3DV42GU
3V3
I2C3_USB 2_SE L
Default
3V3
I2C3
USB 2_PW RF AULT
USB 2_DRVVB US
1
0
GPIO3_23
"1"
Figure 21. I2C diagram
I2C2 should be programmed to be used for SDHC_CD_B and SDHC_WP.
NOTE
The I2C1 bus has an I2C multiplexer (PCA9546APW) to isolate address conflicts and effectively manage large number of I2C
devices. The multiplexer partitions the I2C1 bus into four sub-buses, called "channels". Software must program the multiplexer to
access one of the four I2C1 channels. All boot-software-dependant devices are placed on channel 0, or "I2C1_CH0" as it is
named. Channel 0 is the default selection upon reset so that software has immediate access to critical resources.
The table below shows the I2C bus device map for the FRWY-LS1046A.
Table 20. I2C bus device map
I2C bus 7-bit address Device Description Notes
(All)
- FRWY-LS1046A I2C master
I2C1
0x77 PCA9546APW I2C bus multiplexer (U525)
Converts I2C1 bus into four channels
I2C1_CH
0
0x08 PF8100 Power management
integrated circuit (PMIC)
(U561)
Generates 1 V, 1.8 V, 1.2 V, 1.35 V,
0.6 V, 2.5 V, and 1.8 V
0x40 INA220AIDGST VDD voltage/current/power
monitor (U558)
Reports voltage, current, and power
data for VDD
Table continues on the next page...
FRWY-LS1046A Functional Description
Layerscape FRWY-LS1046A Board Reference Manual, Rev. 0, 26 April 2019
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NXP Semiconductors