Datasheet

Table 20. I2C bus device map (continued)
I2C bus 7-bit address Device Description Notes
0x4C SA56004ED Temperature sensor (U28) Monitors processor thermal diode
0x51 PCF2129AT Battery-backed clock
(U523)
Provides time and date functionality
with battery backup option
0x52 and 0x53 CAT24C04WI-G System ID EEPROM (U524) Stores board-specific data, such as
MAC addresses and serial number /
errata
I2C1_CH
1
I2C address is
defined by the
plugged-in PCIe card
PCIe M.2 slot Key E - based M.2 PCIe x1
slot 1 (J46)
Provides I2C path for J46, which
supports Wi-Fi cards on lane 1 of
SerDes2 controller
I2C1_CH
2
I2C address is
defined by the
plugged-in PCIe card
PCIe M.2 slot Key E - based M.2 PCIe x1
slot 2 (J52)
Provides I2C path for J52, which
supports Wi-Fi cards on lane 3 of
SerDes2 controller
I2C1_CH
3
I2C address is
defined by the
plugged-in click
board
MikroBUS socket MikroBUS socket Provides I2C connectivity to the click
board plugged-in into the mikroBUS
socket
A 7-bit address does not include the read/write (R/W) bit as an address member, though some datasheets might
do so. For consistency, all I2C addresses above are of 7 bits only.
NOTE
The FRWY-LS1046A also provides I2C headers for remotely accessing I2C buses. The table below describes the I2C headers.
Table 21. I2C headers
Part identifier
Header name Header type Purpose
J65 I2C1 1x3 connector To access I2C1 bus remotely
J64 I2C3
1
1x3 connector To access I2C3 bus remotely
J63 I2C4 1x3 connector To access I2C4 bus remotely
1. I2C3_SCL/SDA signals are muxed with USB2_DRVVBUS/PWRFAULT signals and are demuxed with using a multiplexer
NX3DV42GU and controlled using GPIO3_23.
2.12 JTAG header
The FRWY-LS1046A provides an Arm JTAG header, which allows connections with a CodeWarrior TAP for debugging the board.
The figure below shows the JTAG diagram of the FRWY-LS1046A.
JTAG header
Layerscape FRWY-LS1046A Board Reference Manual, Rev. 0, 26 April 2019
NXP Semiconductors
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