Datasheet

LS1046A
TMS
TBSCAN_EN_B
Arm
JTAG
header
FTSH-105-01-L-DV-K
TCK
TDO
TDI
CPU_J TAG_RST_B
CPU_TMS
CPU_TCK
CPU_TDO
CPU_TDI
OVDD
OVDD
8
6
9
7
5
3
4
2
1
10
Reset
control
OVDD
(1.8V)
10K
OVDD
4.7K
10K
Figure 22. JTAG diagram
The table below describes the JTAG header.
Table 22. JTAG header
Part identifier Part number Description Purpose
J15
FTSH-105-01-L-DV-K
10-pin Arm Cortex JTAG
connector
Provides access to the processor
for debugging purposes
2.13 GPIOs
The LS1046A processor has no dedicated general-purpose input/output (GPIO) pins. Instead, GPIO functions are multiplexed
internally onto other signals, which must be disabled before using the GPIO functions. For the FRWY-LS1046A, GPIO access is
provided through the IFC, EC1, and EC2 pins but only when those pins are not used for their primary purposes. The table below
shows the GPIO mapping in the FRWY-LS1046A.
Table 23. GPIO mapping
Processor signal Board function Description
GPIO function Primary function
GPIOs for system configuration
GPIO2_13 IFC_PAR0 BRD_REV0 PCB revision (BRD_REV[1:0]):
• 00: Revision A
• 01: Revision B
GPIO2_14 IFC_PAR1 BRD_REV1
Table continues on the next page...
FRWY-LS1046A Functional Description
Layerscape FRWY-LS1046A Board Reference Manual, Rev. 0, 26 April 2019
36
NXP Semiconductors