Datasheet

Table 23. GPIO mapping (continued)
Processor signal Board function Description
GPIO function Primary function
GPIO3_19 EC2_TX_EN CPU_ID CPU ID (CPU_ID):
• 1: LS1046A CPU
• 0: Others
GPIO2_15 IFC_PERR_B SYS_STATUS# Controls system status LED
GPIO3_21 EC2_GTX_CLK125 uBUS1_PWM Provides PWM input to mikroBUS socket
GPIO3_23 EC2_RXD2 I2C3_USB2_SEL_IO Controls the routing of the I2C3_SCL/SDA and
USB2_DRVVBUS/PWRFAULT signals:
• 0: I2C3_SCL/SDA signals are routed to I2C3
header J64 (default setting)
• 1: USB2_DRVVBUS/PWRFAULT signals are
routed to USB2 port management switch
U550
GPIO3_18 EC2_TXD0 RSV_IO Reserved for general purpose input/output
GPIOs for reset control
GPIO3_25 EC2_RXD0 SW_uBUS1_RST Resets mikroBUS socket
GPIO3_20 EC2_GTX_CLK SW_SLOT1_RST_B Resets M.2 PCIe slot 1
GPIO3_26 EC2_RX_CLK SW_SLOT2_RST_B Resets M.2 PCIe slot 2
GPIO3_27 EC2_RX_DV SW_QSGPHY1_RST_
B
Resets QSGMII PHY
GPIO for fuse programming
GPIO3_24 EC2_RXD1 GPIO_FUSE_PROG Connects to the 1x2 PROG_SFP header (J74).
The GPIO_FUSE_PROG signal controls the
power supply to the TA_PROG_SFP pin of the
processor:
• When GPIO_FUSE_PROG is low, power to
TA_PROG_SFP pin is 1.8 V (fuse
programming enable)
• When GPIO_FUSE_PROG is high, power to
TA_PROG_SFP pin is 0 V (fuse
programming disable) (default value)
GPIO expansion header
GPIO3_06 EC1_TX_EN Connect to a 2x10 GPIO header (J67) for general purpose input/output.
Pin number Signal name Direction (type) I/O voltage
1 GPIO3_06 Bidirectional (input/
output)
1.8 V
GPIO3_11 EC1_RXD1
GPIO3_04 EC1_TXD1
GPIO3_12 EC1_RXD0
GPIO3_02 EC1_TXD3
Table continues on the next page...
GPIOs
Layerscape FRWY-LS1046A Board Reference Manual, Rev. 0, 26 April 2019
NXP Semiconductors
37