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NXP Semiconductors

Data Sheet: Technical Data

Document Number: IMX6DQIEC

Rev. 6, 11/2018

Package Information

FCPBGA Package

21 x 21 mm, 0.8 mm pitch

NXP Reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Ordering Information

See Table 1

MCIMX6QxCxxxxC

MCIMX6QxCxxxxD

MCIMX6QxCxxxxE

MCIMX6DxCxxxxC

MCIMX6DxCxxxxD

MCIMX6DxCxxxxE

1 Introduction

The i.MX 6Dual/6Quad processors represent the latest

achievement in integrated multimedia applications

processors. These processors are part of a growing

family of multimedia-focused products that offer high

performance processing and are optimized for lowest

power consumption.

The i.MX 6Dual/6Quad processors feature advanced

implementation of the quad Arm

Cortex

-A9 core,

which operates at speeds up to 800 MHz. They include

2D and 3D graphics processors, 1080p video processing,

and integrated power management. Each processor

provides a 64-bit DDR3/DDR3L/LPDDR2-800 memory

interface and a number of other interfaces for connecting

peripherals, such as WLAN, Bluetooth

, GPS, hard

drive, displays, and camera sensors.

i.MX 6Dual/6Quad

Applications Processors for

Industrial Products

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Signal Naming Convention . . . . . . . . . . . . . . . . . . . 7

2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 17

3.2 Recommended Connections for Unused Analog

Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . 18

4.2 Power Supplies Requirements and Restrictions . . 31

4.3 Integrated LDO Voltage Regulator Parameters . . 32

4.4 PLL Electrical Characteristics . . . . . . . . . . . . . . . . 34

4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 35

4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 36

4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 41

4.8 Output Buffer Impedance Parameters. . . . . . . . . . 45

4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . 48

4.10 Multi-Mode DDR Controller (MMDC). . . . . . . . . . . 60

4.11 General-Purpose Media Interface (GPMI) Timing. 60

4.12 External Peripheral Interface Parameters . . . . . . . 69

5 Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 130

5.1 Boot Mode Configuration Pins. . . . . . . . . . . . . . . 130

5.2 Boot Devices Interfaces Allocation . . . . . . . . . . . 131

6 Package Information and Contact Assignments . . . . . . 133

6.1 Signal Naming Convention . . . . . . . . . . . . . . . . . 133

6.2 21 x 21 mm Package Information . . . . . . . . . . . . 133

7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Summary of content (162 pages)

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NXP Semiconductors Data Sheet: Technical Data Document Number: IMX6DQIEC Rev. 6, 11/2018 MCIMX6QxCxxxxC MCIMX6QxCxxxxD MCIMX6QxCxxxxE MCIMX6DxCxxxxC MCIMX6DxCxxxxD MCIMX6DxCxxxxE i.MX 6Dual/6Quad Applications Processors for Industrial Products Package Information FCPBGA Package 21 x 21 mm, 0.8 mm pitch Ordering Information See Table 1 1 Introduction The i.MX 6Dual/6Quad processors represent the latest achievement in integrated multimedia applications processors.
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Introduction The i.MX 6Dual/6Quad processors are specifically useful for applications such as the following: The i.MX 6Dual/6Quad processors offers numerous advanced features, such as: • Multilevel memory system—The multilevel memory system of each processor is based on the L1 instruction and data caches, L2 cache, and internal and external memory.
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Introduction Table 1. Example Orderable Part Numbers 1 Part Number Quad/Dual CPU Options Speed1 Grade Temperature Grade MCIMX6Q7CVT08AC i.MX 6Quad Includes VPU, GPU 800 MHz Industrial 21 mm x 21 mm, 0.8 mm pitch, FCPBGA (lidded) MCIMX6Q7CVT08AD i.MX 6Quad Includes VPU, GPU 800 MHz Industrial 21 mm x 21 mm, 0.8 mm pitch, FCPBGA (lidded) MCIMX6Q7CVT08AE i.MX 6Quad Includes VPU, GPU 800 MHz Industrial 21 mm x 21 mm, 0.8 mm pitch, FCPBGA (lidded) MCIMX6D7CVT08AC i.
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Introduction MC IMX6 X @ + VV $$ % A Qualification level MC Silicon revision1 A Prototype Samples PC Rev 1.2 C Mass Production MC Rev 1.3 D Special SC Rev 1.6 E Part # series X Fusing % i.MX 6Quad Q Default setting A D HDCP enabled C $$ i.
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Introduction • • Frequency of the core (including Neon and L1 cache) as per Table 6.
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Introduction • • • – 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max) USB: — One High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY — Three USB 2.0 (480 Mbps) hosts: – One HS host with integrated High Speed PHY – Two HS hosts with integrated High Speed Inter-Chip (HS-IC) USB PHY Expansion PCI Express port (PCIe) v2.0 one lane — PCI Express (Gen 2.
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Introduction • • Support various levels of system power modes Use flexible clock gating control scheme The i.MX 6Dual/6Quad processors use dedicated hardware accelerators to meet the targeted multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance at low power consumption numbers, while having the CPU core relatively free for performing other tasks. The i.
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Architectural Overview 2 Architectural Overview The following subsections provide an architectural overview of the i.MX 6Dual/6Quad processor system. 2.1 Block Diagram Figure 2 shows the functional modules in the i.MX 6Dual/6Quad processor system. Nand-Flash Digital Audio LPDDR2 (400MHz) NOR Flash Battery Ctrl 4x Camera 1 / 2 LVDS Parallel/MIPI (WUXGA+) DDR3 (532MHz) PSRAM Device External Memory Interface GPMI MMDC Internal RAM (272KB) EIM SATA II 3.
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Modules List 3 Modules List The i.MX 6Dual/6Quad processors contain a variety of digital and analog modules. Table 2 describes these modules in alphabetical order. Table 2. i.MX 6Dual/6Quad Modules List Block Mnemonic Block Name Subsystem Brief Description 512 x 8 Fuse Electrical Fuse Array Security Box Electrical Fuse Array. Enables to setup Boot Modes, Security Levels, Security Keys, and many other system parameters. The i.
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Modules List Table 2. i.MX 6Dual/6Quad Modules List (continued) Block Mnemonic Block Name Subsystem Brief Description CSI MIPI CSI-2 Interface Multimedia Peripherals The CSI IP provides MIPI CSI-2 standard camera interface port. The CSI-2 interface supports up to 1 Gbps for up to 3 data lanes and up to 800 Mbps for 4 data lanes. CSU Central Security Unit Security The Central Security Unit (CSU) is responsible for setting comprehensive security policy within the i.MX 6Dual/6Quad platform.
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Modules List Table 2. i.MX 6Dual/6Quad Modules List (continued) Block Mnemonic ESAI FlexCAN-1 FlexCAN-2 GPIO-1 GPIO-2 GPIO-3 GPIO-4 GPIO-5 GPIO-6 GPIO-7 Block Name Subsystem Brief Description Enhanced Serial Audio Interface Connectivity Peripherals The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port for serial communication with a variety of serial devices, including industry-standard codecs, SPDIF transceivers, and other processors.
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Modules List Table 2. i.MX 6Dual/6Quad Modules List (continued) Block Mnemonic GPUVGv2 Block Name Subsystem Brief Description Vector Graphics Processing Unit, ver. 2 Multimedia Peripherals OpenVG graphics accelerator provides OpenVG 1.1 support as well as other accelerations, including Real-time hardware curve tesselation of lines, quadratic and cubic Bezier curves, 16x Line Anti-aliasing, and various Vector Drawing functions.
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Modules List Table 2. i.
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Modules List Table 2. i.MX 6Dual/6Quad Modules List (continued) Block Mnemonic SDMA SJC Block Name Subsystem Brief Description Smart Direct Memory System Access Control Peripherals The SDMA is multi-channel flexible DMA engine. It helps in maximizing system performance by off-loading the various cores in dynamic data routing.
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Modules List Table 2. i.MX 6Dual/6Quad Modules List (continued) Block Mnemonic TEMPMON Block Name Subsystem Brief Description Temperature Monitor System Control Peripherals The temperature monitor/sensor IP module for detecting high temperature conditions. The temperature read out does not reflect case or ambient temperature. It reflects the temperature in proximity of the sensor location on the die.
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Modules List Table 2. i.MX 6Dual/6Quad Modules List (continued) Block Mnemonic uSDHC-1 uSDHC-2 uSDHC-2 uSDHC-4 VDOA VPU WDOG-1 Block Name Subsystem Brief Description SD/MMC and SDXC Connectivity Enhanced Peripherals Multi-Media Card / Secure Digital Host Controller i.MX 6Dual/6Quad specific SoC characteristics: All four MMC/SD/SDIO controller IPs are identical and are based on the uSDHC IP. They are: • Conforms to the SD Host Controller Standard Specification version 3.
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Modules List Table 2. i.MX 6Dual/6Quad Modules List (continued) Block Mnemonic WDOG-2 (TZ) EIM XTALOSC 3.1 Block Name Watchdog (TrustZone) Subsystem Timer Peripherals Brief Description The TrustZone Watchdog (TZ WDOG) timer module protects against TrustZone starvation by providing a method of escaping normal mode and forcing a switch to the TZ mode. TZ starvation is a situation where the normal OS prevents switching to the TZ mode.
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Electrical Characteristics 4 Electrical Characteristics This section provides the device and module-level electrical characteristics for the i.MX 6Dual/6Quad processors. 4.1 Chip-Level Conditions This section provides the device-level electrical characteristics for the SoC. See Table 3 for a quick reference to the individual tables and sections. Table 3. i.MX 6Dual/6Quad Chip-Level Conditions For these characteristics, … 4.1.
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Electrical Characteristics Table 4. Absolute Maximum Ratings Parameter Description Core supply input voltage (LDO enabled) Core supply input voltage (LDO bypass) Core supply output voltage (LDO enabled) VDD_HIGH_IN supply voltage DDR I/O supply voltage GPIO I/O supply voltage HDMI, PCIe, and SATA PHY high (VPH) supply voltage HDMI, PCIe, and SATA PHY low (VP) supply voltage LVDS and MIPI I/O supply voltage (2.
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Electrical Characteristics 4.1.2 Thermal Resistance NOTE Per JEDEC JESD51-2, the intent of thermal resistance measurements is solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. 4.1.2.1 FCPBGA Package Thermal Resistance Table 5 provides the FCPBGA package thermal resistance data. Table 5.
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Electrical Characteristics 4.1.3 Operating Ranges Table 6 provides the operating ranges of the i.MX 6Dual/6Quad processors. Table 6. Operating Ranges Parameter Description Symbol Min Typ Max1 Unit Comment2 VDD_ARM_IN VDD_ARM23_IN3 1.2754 — 1.5 V LDO Output Set Point (VDD_ARM_CAP5) of 1.150 V minimum for operation up to 792 MHz. 1.054 — 1.5 V LDO Output Set Point (VDD_ARM_CAP5) of 0.925 V minimum for operation up to 396 MHz. 1.3504 — 1.
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Electrical Characteristics Table 6. Operating Ranges (continued) Parameter Description GPIO supplies10 HDMI supply voltages PCIe supply voltages SATA Supply voltages Junction temperature 1 2 3 4 5 6 7 8 9 Symbol Min Typ Max1 NVCC_CSI, NVCC_EIM0, NVCC_EIM1, NVCC_EIM2, NVCC_ENET, NVCC_GPIO, NVCC_LCD, NVCC_NANDF, NVCC_SD1, NVCC_SD2, NVCC_SD3, NVCC_JTAG 1.65 1.8, 2.8, 3.3 3.6 NVCC_LVDS_2P511 NVCC_MIPI 2.25 2.5 2.75 V — HDMI_VP 0.99 1.1 1.3 V — HDMI_VPH 2.25 2.5 2.
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Electrical Characteristics 10 All digital I/O supplies (NVCC_xxxx) must be powered under normal conditions whether the associated I/O pins are in use or not, and associated I/O pins need to have a pull-up or pull-down resistor applied to limit any floating gate current. 11 This supply also powers the pre-drivers of the DDR I/O pins; therefore, it must always be provided, even when LVDS is not used. 4.1.4 External Clock Sources Each i.
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Electrical Characteristics — At power up, an internal ring oscillator is used. After crystal oscillator is stable, the clock circuit switches over to the crystal oscillator automatically. — Higher accuracy than ring oscillator. — If no external crystal is present, then the ring oscillator is used. The decision to choose a clock source should be based on real-time clock use and precision timeout. 4.1.5 Maximum Measured Supply Currents Power consumption is highly dependent on the application.
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Electrical Characteristics Table 8. Maximum Supply Currents Maximum Current Power Supply Conditions Unit Power Virus CoreMark i.MX 6Quad: VDD_ARM_IN + VDD_ARM23_IN • ARM frequency = 792 MHz • ARM LDOs set to 1.3V • Tj = 105°C 3270 2090 mA i.MX 6Dual: VDD_ARM_IN • ARM frequency = 792 MHz • ARM LDOs set to 1.3V • Tj = 105°C 1960 1250 mA i.MX 6Dual or i.MX 6Quad: VDD_SOC_IN • GPU frequency = 600 MHz • SOC LDO set to 1.
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Electrical Characteristics Table 8. Maximum Supply Currents (continued) Maximum Current Power Supply Conditions Unit Power Virus CoreMark MISC DRAM_VREF 1 2 3 4 5 — 1 mA The actual maximum current drawn from VDD_HIGH_IN will be as shown plus any additional current drawn from the VDD_HIGH_CAP outputs, depending upon actual application configuration (for example, NVCC_LVDS_2P5, NVCC_MIPI, or HDMI, PCIe, and SATA VPH supplies).
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Electrical Characteristics Table 9. Stop Mode Current and Power Consumption (continued) Mode Test Conditions STOP_OFF STANDBY Deep Sleep Mode (DSM) SNVS Only 1 • • • • • • Arm LDO set to 0.9 V SoC LDO set to 1.225 V PU LDO is power gated HIGH LDO set to 2.5 V PLLs disabled DDR is in self refresh • • • • • • • Arm and PU LDOs are power gated SoC LDO is in bypass HIGH LDO is set to 2.
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Electrical Characteristics 4.1.7 USB PHY Current Consumption 4.1.7.1 Power Down Mode In power down mode, everything is powered down, including the VBUS valid detectors, typical condition. Table 10 shows the USB interface current consumption in power down mode. Table 10. USB PHY Current Consumption in Power Down Mode Current VDD_USB_CAP (3.0 V) VDD_HIGH_CAP (2.5 V) NVCC_PLL_OUT (1.1 V) 5.1 μA 1.7 μA <0.
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Electrical Characteristics Table 11. SATA PHY Current Drain (continued) Mode Test Conditions Supply Typical Current Unit P1: Transmitter idle, Rx powered down, LOS disabled Single Transceiver SATA_VP 0.67 mA SATA_VPH 0.23 SATA_VP 6.9 SATA_VPH 6.2 SATA_VP 0.53 SATA_VPH 0.11 SATA_VP 0.036 SATA_VPH 0.12 SATA_VP 0.13 SATA_VPH 0.012 SATA_VP 0.008 SATA_VPH 0.
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Electrical Characteristics Table 12. PCIe PHY Current Drain (continued) Mode Test Conditions Supply Max Current Unit — PCIE_VP (1.1 V) 12 mA PCIE_VPTX (1.1 V) 2.4 PCIE_VPH (2.5 V) 12 PCIE_VP (1.1 V) 1.3 PCIE_VPTX (1.1 V) 0.18 PCIE_VPH (2.5 V) 0.36 P1: Longer Recovery Time Latency, Lower Power State Power Down 4.1.10 — mA HDMI Maximum Power Consumption Table 13 provides HDMI PHY currents for both Active 3D Tx with LFSR15 data pattern and Power-down modes. Table 13.
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Electrical Characteristics 4.2 Power Supplies Requirements and Restrictions The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to ensure the reliable operation of the device. Any deviation from these sequences may result in the following situations: • Excessive current during power-up phase • Prevention of the device from booting • Irreversible damage to the processor 4.2.
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Electrical Characteristics • power consumption. If boundary scan test is used, SATA_VP and SATA_VPH must remain powered. When the PCIE interface is not used, the PCIE_VP, PCIE_VPH, and PCIE_VPTX supplies should be grounded. The input and output supplies for rest of the ports (PCIE_REXT, PCIE_RX_N, PCIE_RX_P, PCIE_TX_N, and PCIE_TX_P) can remain unconnected. It is recommended not to turn the PCIE_VPH supply OFF while the PCIE_VP supply is ON, as it may lead to excessive power consumption.
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Electrical Characteristics to 1.2 V with the nominal default setting as 1.1 V. The LDO_1P1 supplies the 24 MHz oscillator, PLLs, and USB PHY. A programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded to take the necessary steps. Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed.
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Electrical Characteristics For additional information, see the i.MX 6Dual/6Quad reference manual (IMX6DQRM). 4.4 4.4.1 PLL Electrical Characteristics Audio/Video PLL Electrical Parameters Table 14. Audio/Video PLL Electrical Parameters 4.4.2 Parameter Value Clock output range 650 MHz ~1.3 GHz Reference clock 24 MHz Lock time <11250 reference cycles 528 MHz PLL Table 15. 528 MHz PLL Electrical Parameters 4.4.
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Electrical Characteristics 4.4.5 Arm PLL Table 18. Arm PLL Electrical Parameters 4.5 4.5.1 Parameter Value Clock output range 650 MHz~1.3 GHz Reference clock 24 MHz Lock time <2250 reference cycles On-Chip Oscillators OSC24M This block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implements an oscillator. The oscillator is powered from NVCC_PLL_OUT.
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Electrical Characteristics Table 19. OSC32K Main Characteristics Parameter Min Typ Max Comments Fosc — 32.768 kHz — This frequency is nominal and determined mainly by the crystal selected. 32.0 K would work as well. Current consumption — 4 μA — The typical value shown is only for the oscillator, driven by an external crystal. If the internal ring oscillator is used instead of an external crystal, then approximately 25 μA must be added to this value.
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Electrical Characteristics 4.6.1 XTALI and RTC_XTALI (Clock Inputs) DC Parameters Table 20 shows the DC parameters for the clock inputs. Table 20. XTALI and RTC_XTALI DC Parameters Parameter Symbol Test Conditions XTALI high-level DC input voltage Vih — XTALI low-level DC input voltage Vil — Min Typ Max Unit 0.8 x NVCC_PLL_OUT — NVCC_PLL_ OUT V 0 — 0.2 (See note 1) V RTC_XTALI high-level DC input voltage Vih — 0.8 — RTC_XTALI low-level DC input voltage Vil — 0 — 0.
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Electrical Characteristics Table 21. GPIO I/O DC Parameters (continued) Parameter Symbol Test Conditions Min Max Unit Input current (no pull-up/down) Iin Vin = OVDD or 0 -1 1 μA Input current (22 kΩ pull-up) Iin Vin = 0 V Vin = OVDD — 212 1 μA Input current (47 kΩ pull-up) Iin Vin = 0 V Vin = OVDD — 100 1 μA Input current (100 kΩ pull-up) Iin Vin = 0 V Vin= OVDD — 48 1 μA Input current (100 kΩ pull-down) Iin Vin = 0 V Vin = OVDD — 1 48 μA Rkeep Vin = 0.3 x OVDD Vin = 0.
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Electrical Characteristics Table 22. RGMII I/O 2.5V I/O DC Electrical Parameters1 (continued) Schmitt trigger VT+ 3, 4 VTH+ — 0.5xOVDD — mV Schmitt trigger VT- 3, 4 VTH- — — 0.
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Electrical Characteristics Table 23. LPDDR2 I/O DC Electrical Parameters1 (continued) Parameters Pull-up/pull-down impedance mismatch Symbol Test Conditions Min Max Unit MMpupd — -15 +15 % Rres — — 10 Ω Rkeep — 110 175 kΩ 240 Ω unit calibration resolution Keeper circuit resistance 1 2 Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
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Electrical Characteristics 4.6.5 LVDS I/O DC Parameters The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details. Table 25 shows the Low Voltage Differential Signaling (LVDS) I/O DC parameters. Table 25.
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Electrical Characteristics 4.7.1 General Purpose I/O AC Parameters The I/O AC parameters for GPIO in slow and fast modes are presented in the Table 26 and Table 27, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bits in the IOMUXC control registers. Table 26. General Purpose I/O AC Parameters 1.
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Electrical Characteristics 4.7.2 DDR I/O AC Parameters For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported DDR3/DDR3L/LPDDR2 Configurations.” Table 28 shows the AC parameters for DDR I/O operating in LPDDR2 mode. Table 28. DDR I/O LPDDR2 Mode AC Parameters1 Parameter Symbol Test Condition Min Typ Max Unit Vih(ac) — Vref + 0.22 — OVDD V Vil(ac) — 0 — Vref – 0.22 V AC differential input high voltage Vidh(ac) — 0.
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Electrical Characteristics Table 29. DDR I/O DDR3/DDR3L Mode AC Parameters1 (continued) Parameter Single output slew rate, measured between Vol(ac) and Voh(ac) Skew between pad rise/fall asymmetry + skew caused by SSN Symbol Test Condition Min Typ Max Unit tsr Driver impedance = 34 Ω 2.5 — 5 V/ns tSKD clk = 533 MHz — — 0.1 ns 1 Note that the JEDEC JESD79_3C specification supersedes any specification in this document.
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Electrical Characteristics 4.8 Output Buffer Impedance Parameters This section defines the I/O impedance parameters of the i.MX 6Dual/6Quad processors for the following I/O types: • General Purpose I/O (GPIO) • Double Data Rate I/O (DDR) for LPDDR2, and DDR3 modes • LVDS I/O NOTE GPIO and DDR I/O output driver impedance is measured with “long” transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission line.
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Electrical Characteristics OVDD PMOS (Rpu) Ztl Ω, L = 20 inches ipp_do pad predriver Cload = 1p NMOS (Rpd) OVSS U,(V) Vin (do) VDD t,(ns) 0 U,(V) Vout (pad) OVDD Vref2 Vref1 Vref t,(ns) 0 Vovdd – Vref1 Rpu = Vref1 Rpd = Vref2 × Ztl × Ztl Vovdd – Vref2 Figure 7. Impedance Matching Load for Measurement i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev.
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Electrical Characteristics 4.8.1 GPIO Output Buffer Impedance Table 31 shows the GPIO output buffer impedance (OVDD 1.8 V). Table 31. GPIO Output Buffer Average Impedance (OVDD 1.8 V) Parameter Output Driver Impedance Symbol Drive Strength (DSE) Typ Value Unit Rdrv 001 010 011 100 101 110 111 260 130 90 60 50 40 33 Ω Table 32 shows the GPIO output buffer impedance (OVDD 3.3 V). Table 32. GPIO Output Buffer Average Impedance (OVDD 3.
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Electrical Characteristics 4.8.2 DDR I/O Output Buffer Impedance For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported DDR3/DDR3L/LPDDR2 Configurations.” Table 33 shows DDR I/O output buffer impedance of i.MX 6Dual/6Quad processors. Table 33. DDR I/O Output Buffer Impedance Typical Parameter Output Driver Impedance Symbol Test Conditions Rdrv Drive Strength (DSE) = 000 001 010 011 100 101 110 111 NVCC_DRAM=1.5 V (DDR3) DDR_SEL=11 NVCC_DRAM=1.
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Electrical Characteristics Table 34. Reset Timing Parameters ID CC1 4.9.2 Parameter Duration of SRC_POR_B to be qualified as valid Min Max Unit 1 — XTALOSC_RTC_ XTALI cycle WDOG Reset Timing Parameters Figure 9 shows the WDOG reset timing and Table 35 lists the timing parameters. WDOG1_B (Output) CC3 Figure 9. WDOG1_B Timing Diagram Table 35.
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Electrical Characteristics 4.9.3.1 EIM Interface Pads Allocation EIM supports 32-bit, 16-bit and 8-bit devices operating in address/data separate or multiplexed modes. Table 36 provides EIM interface pads allocation in different modes. Table 36.
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Electrical Characteristics 4.9.3.2 General EIM Timing-Synchronous Mode Figure 10, Figure 11, and Table 37 specify the timings related to the EIM module. All EIM output control signals may be asserted and deasserted by an internal clock synchronized to the EIM_BCLK rising edge according to corresponding assertion/negation control fields. WE2 EIM_BCLK ...
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Electrical Characteristics Table 37. EIM Bus Timing Parameters (continued) ID 1 2 Parameter Min1 Max1 Unit WE4 Clock rise to address valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns WE5 Clock rise to address invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns WE6 Clock rise to EIM_CSx_B valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns WE7 Clock rise to EIM_CSx_B invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns WE8 Clock rise to EIM_WE_B valid -0.
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Electrical Characteristics Figure 12 to Figure 15 provide few examples of basic EIM accesses to external memory devices with the timing parameters mentioned previously for specific control parameters settings. EIM_BCLK EIM_ADDRxx WE5 WE4 Address v1 Last Valid Address WE6 WE6 WE7 EIM_CSx_B EIM_WE_B WE14 WE15 EIM_LBA_B WE10 WE11 WE12 WE13 EIM_OE_B EIM_EBx_B WE18 WE19 D(v1) EIM_DATAxx Figure 12.
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Electrical Characteristics EIM_BCLK EIM_ADDRxx/ EIM_ADxx Last Valid Address EIM_CSx_B EIM_WE_B WE17 WE16 WE5 WE4 Write Data Address V1 WE6 WE7 WE8 WE9 WE15 WE14 EIM_LBA_B EIM_OE_B WE10 WE11 EIM_EBx_B Figure 14. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6,ADVA=0, ADVN=1, and ADH=1 NOTE In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the data bus.
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Electrical Characteristics 4.9.3.4 General EIM Timing-Asynchronous Mode Figure 16 through Figure 20 and Table 38 provide timing parameters relative to the chip select (CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the timing parameters mentioned above. Asynchronous read and write access length in cycles may vary from what is shown in Figure 16 through Figure 19 as RWSC, OEN & CSN is configured differently. See the i.
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Electrical Characteristics end of access start of access INT_CLK MAXCSO EIM_CSx_B MAXDI WE31 EIM_ADDRxx/ EIM_ADxx D(V1) Addr. V1 WE44 WE32A EIM_WE_B WE40A WE39 EIM_LBA_B WE35A WE36 EIM_OE_B WE37 EIM_EBx_B WE38 MAXCO Figure 17. Asynchronous A/D Muxed Read Access (RWSC = 5) EIM_CSx_B WE31 EIM_ADDRxx Last Valid Address WE32 Next Address Address V1 WE33 WE34 WE39 WE40 WE45 WE46 EIM_WE_B EIM_LBA_B EIM_OE_B EIM_EBx_B WE42 EIM_DATAxx WE41 D(V1) Figure 18.
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Electrical Characteristics EIM_CSx_B WE31 EIM_ADDRxx/ EIM_DATAxx WE41A D(V1) Addr. V1 WE42 WE32A WE33 WE34 EIM_WE_B WE39 EIM_LBA_B WE40A EIM_OE_B WE45 WE46 EIM_EBx_B Figure 19. Asynchronous A/D Muxed Write Access EIM_CSx_B WE31 EIM_ADDRxx Last Valid Address WE32 Next Address Address V1 EIM_WE_B WE39 WE40 WE35 WE36 WE37 WE38 EIM_LBA_B EIM_OE_B EIM_EBx_B WE44 D(V1) EIM_DATAxx[07:00] WE43 WE48 EIM_DTACK_B WE47 Figure 20. DTACK Mode Read Access (DAP=0) i.
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Electrical Characteristics EIM_CSx_B WE31 EIM_ADDRxx Last Valid Address WE32 Next Address Address V1 WE33 WE34 WE39 WE40 WE45 WE46 EIM_WE_B EIM_LBA_B EIM_OE_B EIM_EBx_B WE42 EIM_DATAxx WE41 D(V1) WE48 EIM_DTACK_B WE47 Figure 21. DTACK Mode Write Access (DAP=0) Table 38. EIM Asynchronous Timing Parameters Relative to Chip Select1, 2 Ref No. Parameter Determination by Synchronous measured parameters Min Max Unit WE31 EIM_CSx_B valid to Address Valid WE4-WE6-CSA×t -3.5-CSA×t 3.
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Electrical Characteristics Table 38. EIM Asynchronous Timing Parameters Relative to Chip Select1, 2 (continued) Ref No. WE40 Parameter EIM_LBA_B Invalid to EIM_CSx_B Invalid (ADVL is asserted) Determination by Synchronous measured parameters Min Max Unit WE7-WE15-CSN×t -3.5-CSN×t 3.5-CSN×t ns 3.5+(ADVN+ADVA +1-CSA)×t ns 3.5-WCSA×t ns WE40A EIM_CSx_B Valid to EIM_LBA_B WE14-WE6+(ADVN+ADVA+1- -3.
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Electrical Characteristics 2 In this table: • t means clock period from axi_clk frequency. • CSA means register setting for WCSA when in write operations or RCSA when in read operations. • CSN means register setting for WCSN when in write operations or RCSN when in read operations. • ADVN means register setting for WADVN when in write operations or RADVN when in read operations. • ADVA means register setting for WADVA when in write operations or RADVA when in read operations. 4.
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Electrical Characteristics 4.11.1 Asynchronous Mode AC Timing (ONFI 1.0 Compatible) Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The Maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. Figure 22 through Figure 25 depict the relative timing between GPMI signals at the module level for different operations under Asynchronous mode. Table 40 describes the timing parameters (NF1–NF17) that are shown in the figures. .!.$?#% ?" NF2 NF1 .!.
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Electrical Characteristics .!.$?#,% .!.$?#% ?" NF14 .!.$?2%?" .!.$?2%!$9?" NF15 NF13 NF12 NF16 .!.$?$!4!XX NF17 Data from NF Figure 25. Read Data Latch Cycle Timing Diagram (Non-EDO Mode) .!.$?#,% .!.$?#% ?" NF14 NF13 .!.$?2%?" .!.$?2%!$9?" NF15 NF12 NF17 NF16 NAND_DATAxx Data from NF Figure 26. Read Data Latch Cycle Timing Diagram (EDO Mode) Table 40.
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Electrical Characteristics Table 40. Asynchronous Mode Timing Parameters1 (continued) ID 1 2 3 4 5 6 Parameter Timing T = GPMI Clock Cycle Symbol Unit Min Max NF16 Data setup on read tDSR — (DS × T -0.67)/18.38 [see 5,6] ns NF17 Data hold on read tDHR 0.82/11.83 [see 5,6] — ns The GPMI asynchronous mode output timing can be controlled by the module’s internal registers HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
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Electrical Characteristics 4.11.2 Source Synchronous Mode AC Timing (ONFI 2.x Compatible) Figure 27 shows the write and read timing of Source Synchronous mode. .!.$?#%?" NF19 NF18 NF23 NAND_CLE NF25 NF26 NF24 NAND_ALE NF25 NF26 NAND_WE/RE_B NF22 NAND_CLK NAND_DQS NAND_DQS Output enable NF20 NF20 NF21 NF21 NAND_DATA[7:0] CMD ADD NAND_DATA[7:0] Output enable Figure 27. Source Synchronous Mode Command and Address Timing Diagram i.
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Electrical Characteristics .!.$?#% ?" NF19 NF18 NF23 .!.$?#,% NF23 .!.$?!,% NF25 NF26 NF25 NF26 NF24 NF24 NAND_WE/RE_B NF22 .!.$?#,+ NF27 NF27 .!.$?$13 .!.$?$13 Output enable NF29 NF29 .!.$?$1; = NF28 NF28 .!.$?$1; = Output enable Figure 28. Source Synchronous Mode Data Write Timing Diagram NF18 .!.$?#%?" NF19 NF23 .!.$?#,% NF23 NAND_ALE NF25 NF26 NF25 NF26 NF24 NF24 NF25 .!.$?7% 2% NF25 NF22 NF26 .!.$?#,+ .!.$?$13 .!.$?$13 /UTPUT ENABLE .!.$?$!4!; = .!.
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Electrical Characteristics .!.$?$13 NF30 .!.$?$!4!; = D0 NF30 D1 D2 D3 NF31 NF31 Figure 30. NAND_DQS/NAND_DQ Read Valid Window Table 41. Source Synchronous Mode Timing Parameters1 ID Parameter Symbol Timing T = GPMI Clock Cycle Min NF18 NAND_CEx_B access time NF19 NAND_CEx_B hold time tCE tCH Unit Max CE_DELAY × T - 0.79 [see 2] 0.5 × tCK - 0.63 [see 2] ns ns NF20 Command/address NAND_DATAxx setup time tCAS 0.5 × tCK - 0.05 ns NF21 Command/address NAND_DATAxx hold time tCAH 0.
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Electrical Characteristics 4.11.3 4.11.3.1 Samsung Toggle Mode AC Timing Command and Address Timing Samsung Toggle mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing. See Section 4.11.1, “Asynchronous Mode AC Timing (ONFI 1.0 Compatible)” for details. 4.11.3.2 Read and Write Timing DEV?CLK .!.$?#%X?" .!.$?#,% .!.$?!,% .!.$?7%?" .!.$?2%?" .& .& .!.$?$13 .!.$?$!4!; = T#+ T#+ Figure 31. Samsung Toggle Mode Data Write Timing i.
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Electrical Characteristics DEV?CLK .!.$?#%X?" .& .!.$?#,% .!.$?!,% .!.$?7%?" T #+ .& T #+ .& .!.$?2%?" T #+ T #+ T #+ .!.$?$13 .!.$?$!4!; = Figure 32. Samsung Toggle Mode Data Read Timing Table 42.
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Electrical Characteristics Table 42. Samsung Toggle Mode Timing Parameters1 (continued) ID 1 2 3 4 5 6 7 Parameter Symbol Timing T = GPMI Clock Cycle Unit Min Max NF28 Data write setup 6 tDS 0.25 × tCK - 0.32 — ns NF29 Data write hold tDH6 0.25 × tCK - 0.79 — ns NF30 NAND_DQS/NAND_DQ read setup skew tDQSQ7 — 3.18 — NF31 NAND_DQS/NAND_DQ read hold skew tQHS7 — 3.
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Electrical Characteristics 4.12.2.1 ECSPI Master Mode Timing Figure 33 depicts the timing of ECSPI in master mode and Table 43 lists the ECSPI master mode timing characteristics. ECSPIx_RDY_B CS10 ECSPIx_SS_B CS1 CS2 CS3 CS5 CS6 CS4 ECSPIx_SCLK CS7 CS2 CS3 ECSPIx_MOSI CS8 CS9 ECSPIx_MISO Note: ECSPIx_MOSI is always driven (not tri-stated) between actual data transmissions. This limits the ECSPI to be connected between a single master and a single slave. Figure 33.
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Electrical Characteristics 4.12.2.2 ECSPI Slave Mode Timing Figure 34 depicts the timing of ECSPI in slave mode and Table 44 lists the ECSPI slave mode timing characteristics. ECSPIx_SS_B CS2 CS1 CS5 CS6 CS4 ECSPIx_SCLK CS2 CS9 ECSPIx_MISO CS8 CS7 ECSPIx_MOSI Note: ECSPIx_MISO is always driven (not tri-stated) between actual data transmissions. This limits the ECSPI to be connected between a single master and a single slave. Figure 34. ECSPI Slave Mode Timing Diagram Table 44.
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Electrical Characteristics 4.12.3 Enhanced Serial Audio Interface (ESAI) Timing Parameters The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. Table 45 shows the interface timing values. The number field in the table refers to timing signals found in Figure 35 and Figure 36. Table 45. Enhanced Serial Audio Interface (ESAI) Timing Parameter1,2 ID Symbol Expression2 Min Max Condition3 Unit tSSICC 4 × Tc 4 × Tc 30.0 30.
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Electrical Characteristics Table 45. Enhanced Serial Audio Interface (ESAI) Timing (continued) 1 2 3 4 5 6 ID Parameter1,2 Symbol Expression2 Min Max Condition3 Unit 81 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr) low5 — — — — — — 22.0 12.0 x ck i ck ns 82 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) high — — — — — — 19.0 9.0 x ck i ck ns 83 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) low — — — — — — 20.0 10.
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Electrical Characteristics 62 63 64 ESAI_TX_CLK (Input/Output) 78 ESAI_TX_FS (Bit) Out 79 82 ESAI_TX_FS (Word) Out 83 86 86 84 87 First Bit Data Out Last Bit 89 ESAI_TX_FS (Bit) In 91 90 91 ESAI_TX_FS (Word) In Figure 35. ESAI Transmitter Timing i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev.
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Electrical Characteristics 62 63 64 ESAI_RX_CLK (Input/Output) 65 ESAI_RX_FS (Bit) Out 66 69 70 ESAI_RX_FS (Word) Out 72 71 First Bit Data In Last Bit 75 73 ESAI_RX_FS (Bit) In 74 75 ESAI_RX_FS (Word) In Figure 36. ESAI Receiver Timing i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev.
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Electrical Characteristics Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) 4.12.4 AC Timing This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single Data Rate) timing and eMMC4.4/4.1 (Dual Date Rate) timing. 4.12.4.1 SD/eMMC4.3 (Single Data Rate) AC Timing Figure 37 depicts the timing of SD/eMMC4.3, and Table 46 lists the SD/eMMC4.3 timing characteristics.
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Electrical Characteristics Table 46. SD/eMMC4.3 Interface Timing Specification (continued) ID Parameter Symbols Min Max Unit eSDHC Input/Card Outputs SD_CMD, SD_DATAx (Reference to SDx_CLK) SD7 eSDHC Input Setup Time SD8 4 eSDHC Input Hold Time tISU 2.5 — ns tIH 1.5 — ns 1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz.
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Electrical Characteristics 4.12.4.3 SDR50/SDR104 AC Timing Figure 39 depicts the timing of SDR50/SDR104, and Table 48 lists the SDR50/SDR104 timing characteristics. SD1 SD2 SD3 SCK SD5 SD4 Output from uSDHC to card SD7 SD6 Input from card to uSDHC SD8 Figure 39. SDR50/SDR104 Timing Table 48. SDR50/SDR104 Interface Timing Specification ID Parameter Symbols Min Max Unit Card Input Clock SD1 Clock Frequency Period tCLK 4.8 — ns SD2 Clock Low Time tCL 0.46 × tCLK 0.
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Electrical Characteristics 4.12.4.4 Bus Operation Condition for 3.3 V and 1.8 V Signaling Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50 mode is 1.8 V. The DC parameters for the NVCC_SD1, NVCC_SD2, and NVCC_SD3 supplies are identical to those shown in Table 21, “GPIO I/O DC Parameters,” on page 37. 4.12.5 Ethernet Controller (ENET) AC Electrical Specifications 4.12.5.
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Electrical Characteristics 4.12.5.1.2 MII Transmit Signal Timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN, ENET_TX_ER, and ENET_TX_CLK) The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the ENET_TX_CLK frequency. Figure 41 shows MII transmit signal timings. Table 50 describes the timing parameters (M5–M8) shown in the figure.
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Electrical Characteristics Table 51. MII Asynchronous Inputs Signal Timing ID M91 1 Characteristic ENET_CRS to ENET_COL minimum pulse width Min Max Unit 1.5 — ENET_TX_CLK period ENET_COL has the same timing in 10-Mbit 7-wire interface mode. 4.12.5.1.4 MII Serial Management Channel Timing (ENET_MDIO and ENET_MDC) The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3 MII specification.
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Electrical Characteristics 4.12.5.2 RMII Mode Timing In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference clock. ENET_RX_EN is used as the ENET_RX_EN in RMII. Other signals under RMII mode include ENET_TX_EN, ENET0_TXD[1:0], ENET_RXD[1:0] and ENET_RX_ER. Figure 44 shows RMII mode timings. Table 53 describes the timing parameters (M16–M21) shown in the figure.
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Electrical Characteristics 4.12.5.3 RGMII Signal Switching Specifications The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver devices. Table 54. RGMII Signal Switching Specifications1 Symbol Tcyc2 Description Clock cycle duration TskewT3 Data to clock output skew at transmitter TskewR3 Min Max Unit 7.2 8.8 ns -100 900 ps Data to clock input skew at receiver 1 2.
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Electrical Characteristics Figure 46. RGMII Receive Signal Timing Diagram Original Figure 47. RGMII Receive Signal Timing Diagram with Internal Delay 4.12.6 Flexible Controller Area Network (FlexCAN) AC Electrical Specifications The Flexible Controller Area Network (FlexCAN) module is a communication controller implementing the CAN protocol according to the CAN 2.0B protocol specification.The processor has two CAN modules available for systems design.
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Electrical Characteristics Power-up time for the HDMI 3D Tx PHY while operating with the fastest input reference clock supported (340 MHz) is 133 μs. 4.12.7.2 Electrical Characteristics The table below provides electrical characteristics for the HDMI 3D Tx PHY. The following three figures illustrate various definitions and measurement conditions specified in the table below. Figure 48. Driver Measuring Conditions Figure 49. Driver Definitions Figure 50. Source Termination Table 55.
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Electrical Characteristics Table 55. Electrical Characteristics (continued) Symbol RT Parameter Termination resistance Condition Min Typ Max Unit — 45 50 55 Ω TMDS drivers DC specifications VOFF VSWING VH VL RTERM RT = 50 Ω For measurement conditions and Single-ended output swing voltage definitions, see the first two figures above. Compliance point TP1 as defined in the HDMI specification, version 1.3a, section 4.2.4.
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Electrical Characteristics PTMDSCLK 50% tCPL tCPH Figure 51. TMDS Clock Signal Definitions Figure 52. Eye Diagram Mask Definition for HDMI Driver Signal Specification at TP1 Figure 53. Intra-Pair Skew Definition i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev.
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Electrical Characteristics Figure 54. Inter-Pair Skew Definition Figure 55. TMDS Output Signals Rise and Fall Time Definition Table 56. Switching Characteristics Symbol Parameter Conditions Min Typ Max Unit — — 3.4 Gbps 25 — 340 MHz 2.94 — 40 ns 40 50 60 % TMDS Drivers Specifications — F TMDSCLK P TMDSCLK t CDC t — TMDSCLK frequency On TMDSCLKP/N outputs TMDSCLK period RL = 50 Ω See Figure 51. TMDSCLK duty cycle t CDC =t CPH /P TMDSCLK RL = 50 Ω See Figure 51.
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Electrical Characteristics Table 56. Switching Characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit 75 — 0.4 UI ps tF Differential output signal fall time 20–80% RL = 50 Ω See Figure 55. — Differential signal overshoot Referred to 2x VSWING — — 15 % — Differential signal undershoot Referred to 2x VSWING — — 25 % — — 3.
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Electrical Characteristics Table 57. I2C Module Timing Parameters (continued) Standard Mode ID IC9 Fast Mode Parameter Bus free time between a STOP and START condition Unit Min Max Min 4.7 — 1.3 Max — µs 4 300 ns IC10 Rise time of both I2Cx_SDA and I2Cx_SCL signals — 1000 20 + 0.1Cb IC11 Fall time of both I2Cx_SDA and I2Cx_SCL signals — 300 20 + 0.
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Electrical Characteristics 4.12.10.1 IPU Sensor Interface Signal Mapping The IPU supports a number of sensor input formats. Table 58 defines the mapping of the Sensor Interface Pins used for various supported interface formats. Table 58.
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Electrical Characteristics 2 3 4 5 6 7 8 The MSB bits are duplicated on LSB bits implementing color extension. The two MSB bits are duplicated on LSB bits implementing color extension. YCbCr, 8 bits—Supported within the BT.656 protocol (sync embedded within the data stream). RGB, 16 bits—Supported in two ways: (1) As a “generic data” input—with no on-the-fly processing; (2) With on-the-fly processing, but only under some restrictions on the control protocol.
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Electrical Characteristics stops receiving data from the stream. For the next line, the IPU2_CSIx_HSYNC timing repeats. For the next frame, the IPU2_CSIx_VSYNC timing repeats. 4.12.10.2.3 Non-Gated Clock Mode The timing is the same as the gated-clock mode (described in Section 4.12.10.2.2, “Gated Clock Mode,”) except for the IPU2_CSIx_HSYNC signal, which is not used (see Figure 58). All incoming pixel clocks are valid and cause data to be latched into the input FIFO.
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Electrical Characteristics 4.12.10.3 Electrical Characteristics Figure 59 depicts the sensor interface timing. IPU2_CSIx_PIX_CLK signal described here is not generated by the IPU. Table 59 lists the sensor interface timing characteristics. IPUx_CSIx_PIX_CLK (Sensor Output) IP3 1/IP1 IP2 IPUx_CSIx_DATA_EN, IPUx_CSIx_VSYNC, IPUx_CSIx_HSYNC Figure 59. Sensor Interface Timing Diagram Table 59.
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Electrical Characteristics Table 60. Video Signal Cross-Reference (continued) i.
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Electrical Characteristics Table 60. Video Signal Cross-Reference (continued) i.
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Electrical Characteristics There are special physical outputs to provide synchronous controls: • The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display (component, pixel) clock for a display. • The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide HSYNC, VSYNC, DRDY or any else independent signal to a display. The IPU has a system of internal binding counters for internal events (such as, HSYNC/VSYNC) calculation.
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Electrical Characteristics 4.12.10.6.2 LCD Interface Functional Description Figure 60 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure, signals are shown with negative polarity. The sequence of events for active matrix interface timing is: • DI_CLK internal DI clock is used for calculation of other controls. • IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected). In active mode, IPP_DISP_CLK runs continuously.
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Electrical Characteristics IP13o IP7 IP5o IP8o IP5 IP8 DI clock IPP_DISP_CLK VSYNC HSYNC DRDY IPP_DATA D0 local start point local start point Dn IP9o IP9 local start point D1 IP10 IP6 Figure 61. TFT Panels Timing Diagram—Horizontal Sync Pulse Figure 62 depicts the vertical timing (timing of one frame). All parameters shown in the figure are programmable. Start of frame End of frame IP13 VSYNC DRDY IP11 HSYNC IP15 IP14 IP12 Figure 62. TFT Panels Timing Diagram—Vertical Sync Pulse i.
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Electrical Characteristics Table 61 shows timing characteristics of signals presented in Figure 61 and Figure 62. Table 61.
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Electrical Characteristics Table 61. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued) ID Symbol Value Todicp DISP_CLK_OFFSET × Tdiclk IP13o Offset of VSYNC Tovs IP8o Offset of HSYNC IP9o Offset of DRDY IP5o 1 Parameter Offset of IPP_DISP_CLK Description Unit DISP_CLK_OFFSET—offset of IPP_DISP_CLK edges from local start point, in DI_CLK×2 (0.5 DI_CLK Resolution). Defined by DISP_CLK counter.
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Electrical Characteristics Figure 63 depicts the synchronous display interface timing for access level. The DISP_CLK_DOWN and DISP_CLK_UP parameters are register-controlled. Table 62 lists the synchronous display interface timing characteristics. IP20o IP20 VSYNC HSYNC DRDY other controls IPP_DISP_CLK Tdicu Tdicd IPP_DATA IP16 IP17 IP19 IP18 local start point Figure 63. Synchronous Display Interface Timing Diagram—Access Level Table 62.
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Electrical Characteristics 4.12.11 LVDS Display Bridge (LDB) Module Parameters The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits.” Table 63.
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Electrical Characteristics Table 64. Electrical and Timing Information (continued) Symbol Parameters Test Conditions Min Typ Max Unit HS Line Drivers DC Specifications |VOD| HS Transmit Differential output voltage magnitude 80 Ω<= RL< = 125 Ω 140 200 270 mV Δ|VOD| Change in Differential output voltage magnitude between logic states 80 Ω<= RL< = 125 Ω — — 10 mV VCMTX Steady-state common-mode output voltage.
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Electrical Characteristics Table 64. Electrical and Timing Information (continued) Symbol Parameters Test Conditions Min Typ Max Unit LP Line Receiver DC Specifications VIL Input low voltage — — — 550 mV VIH Input high voltage — 920 — — mV VHYST Input hysteresis — 25 — — mV 200 — 450 mV Contention Line Receiver DC Specifications VILF Input low fault threshold — 4.12.12.
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Electrical Characteristics 4.12.12.3 HS Line Driver Characteristics Ideal Single-Ended High Speed Signals VDN VCMTX = (VDP + VDN)/2 VOD(0) VOD(1) VDP Ideal Differential High Speed Signals VOD(1) 0V (Differential) VOD(0) VOD = VDP - VDN Figure 65. Ideal Single-ended and Resulting Differential HS Signals 4.12.12.
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Electrical Characteristics Table 65. Electrical and Timing Information (continued) Symbol Parameters Test Conditions tCDC = tCPH / PDDRCLK Min Typ Max Unit — 50 — % tCDC DDR CLK duty cycle tCPH DDR CLK high time — — 1 — UI tCPL DDR CLK low time — — 1 — UI — DDR CLK / DATA Jitter — — 75 — ps pk-pk tSKEW[PN] Intra-Pair (Pulse) skew — — 0.075 — UI tSKEW[TX] Data to Clock Skew — 0.350 — 0.
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Electrical Characteristics Table 65. Electrical and Timing Information (continued) Symbol Parameters Test Conditions Min Typ Max Unit LS Equivalent wire bond series inductance — — — 1.5 nH RS Equivalent wire bond series resistance — — — 0.15 Ω RL Load Resistance — 80 100 125 Ω 4.12.12.6 High-Speed Clock Timing CLKp CLKn 1 Data Bit Time = 1UI 1 Data Bit Time = 1UI UIINST(1) UIINST(2) 1 DDR Clock Period = UIINST(1) + UIINST(2) Figure 67. DDR Clock Definition 4.12.12.
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Electrical Characteristics 4.12.12.9 Low-Power Receiver Timing 2*TLPX eSPIKE 2*TLPX Input TMIN-RX eSPIKE TMIN-RX VIH VIL Output Figure 70. Input Glitch Rejection of Low-Power Receivers 4.12.13 HSI Host Controller Timing Parameters This section describes the timing parameters of the HSI Host Controller which are compliant with High-Speed Synchronous Serial Interface (HSI) Physical Layer specification version 1.01. 4.12.13.
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Electrical Characteristics 4.12.13.3 Receiver Real-Time Data Flow First bit of frame t Last bit of frame First bit of frame Last bit of frame NomBit DATA FLAG N-bits Frame N-bits Frame READY Receiver has detected the start of the Frame Receiver has captured a complete Frame Figure 73. Receiver Real-Time Data Flow READY Signal Timing 4.12.13.4 Synchronized Data Flow Transmission with Wake TX state A B C PHY Frame A D PHY Frame DATA FLAG 3. First bit received READY WAKE RX state 1.
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Electrical Characteristics 4.12.13.6 Frame Transmission Mode (Synchronized Data Flow) Frame start bit Channel Description bits Payload Data Bits DATA FLAG Complete N-bits Frame Complete N-bits Frame READY Figure 76. Frame Transmission Mode Transfer of Two Frames (Synchronized Data Flow) 4.12.13.7 Frame Transmission Mode (Pipelined Data Flow) Frame start bit Channel Description bits Payload Data Bits DATA FLAG Complete N-bits Frame Complete N-bits Frame READY Figure 77.
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Electrical Characteristics 4.12.13.9 DATA and FLAG Signal Timing t DATA (TX) 50% t 50% t 50% Note2 Rise 80% 80% 20% t Bit t DATA (RX) 80% 50% Note1 FLAG (TX) EdgeSepTx 20% 20% Fall t TxToRxSkew EdgeSepRx 80% 50% Note2 Note1 50% FLAG (RX) 20% Figure 78. DATA and FLAG Signal Timing 4.12.14 PCIe PHY Parameters The PCIe interface complies with PCIe specification Gen2 x1 lane and supports the PCI Express 1.1/2.0 standard. 4.12.14.
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Electrical Characteristics 4.12.16 SATA PHY Parameters This section describes SATA PHY electrical specifications. 4.12.16.1 Transmitter and Receiver Characteristics The SATA PHY meets or exceeds the electrical compliance requirements defined in the SATA specifications. NOTE The tables in the following sections indicate any exceptions to the SATA specification or aspects of the SATA PHY that exceed the standard, as well as provide information about parameters not defined in the standard.
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Electrical Characteristics 4.12.17 SCAN JTAG Controller (SJC) Timing Parameters Figure 80 depicts the SJC test clock input timing. Figure 81 depicts the SJC boundary scan timing. Figure 82 depicts the SJC test access port. Figure 83 depicts the JTAG_TRST_B timing. Signal parameters are listed in Table 70. SJ1 SJ2 JTAG_TCK (Input) SJ2 VM VIH VM VIL SJ3 SJ3 Figure 80.
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Electrical Characteristics JTAG_TCK (Input) VIH VIL SJ8 JTAG_TDI JTAG_TMS (Input) SJ9 Input Data Valid SJ10 JTAG_TDO (Output) Output Data Valid SJ11 JTAG_TDO (Output) SJ10 JTAG_TDO (Output) Output Data Valid Figure 82. Test Access Port Timing Diagram JTAG_TCK (Input) JTAG_TRST_B (Input) SJ13 SJ12 Figure 83. JTAG_TRST_B Timing Diagram Table 70.
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Electrical Characteristics Table 70. JTAG Timing (continued) All Frequencies Parameter1,2 ID 1 2 Unit Min Max SJ9 JTAG_TMS, JTAG_TDI data hold time 25 — ns SJ10 JTAG_TCK low to JTAG_TDO data valid — 44 ns SJ11 JTAG_TCK low to JTAG_TDO high impedance — 44 ns SJ12 JTAG_TRST_B assert time 100 — ns SJ13 JTAG_TRST_B set-up time to JTAG_TCK low 40 — ns TDC = target frequency of SJC VM = mid-point voltage 4.12.
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Electrical Characteristics srckp srckpl SPDIF_SR_CLK srckph VM VM (Output) Figure 84. SPDIF_SR_CLK Timing Diagram stclkp stclkpl SPDIF_ST_CLK stclkph VM VM (Input) Figure 85. SPDIF_ST_CLK Timing Diagram 4.12.19 SSI Timing Parameters This section describes the timing parameters of the SSI module. The connectivity of the serial synchronous interfaces are summarized in Table 72. Table 72.
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Electrical Characteristics 4.12.19.1 SSI Transmitter Timing with Internal Clock Figure 86 depicts the SSI transmitter internal clock timing and Table 73 lists the timing parameters for the SSI transmitter internal clock. . SS1 SS3 SS5 SS2 SS4 AUDx_TXC (Output) SS8 SS6 AUDx_TXFS (bl) (Output) SS10 SS12 SS14 AUDx_TXFS (wl) (Output) SS15 SS16 SS18 SS17 AUDx_TXD (Output) SS43 SS42 SS19 AUDx_RXD (Input) Note: AUDx_RXD input in synchronous mode only Figure 86.
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Electrical Characteristics Table 73. SSI Transmitter Timing with Internal Clock (continued) ID Parameter Min Max Unit Synchronous Internal Clock Operation SS42 AUDx_RXD setup before AUDx_TXC falling 10.0 — ns SS43 AUDx_RXD hold after AUDx_TXC falling 0.0 — ns • • • • NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0).
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Electrical Characteristics 4.12.19.2 SSI Receiver Timing with Internal Clock Figure 87 depicts the SSI receiver internal clock timing and Table 74 lists the timing parameters for the receiver timing with the internal clock. SS1 SS3 SS5 SS2 SS4 AUDx_TXC (Output) SS9 SS7 AUDx_TXFS (bl) (Output) SS11 SS13 AUDx_TXFS (wl) (Output) SS20 SS21 AUDx_RXD (Input) SS47 SS48 SS51 SS49 SS50 AUDx_RXC (Output) Figure 87. SSI Receiver Internal Clock Timing Diagram Table 74.
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Electrical Characteristics Table 74. SSI Receiver Timing with Internal Clock (continued) ID Parameter Min Max Unit 15.04 — ns Oversampling Clock Operation SS47 Oversampling clock period SS48 Oversampling clock high period 6.0 — ns SS49 Oversampling clock rise time — 3.0 ns SS50 Oversampling clock low period 6.0 — ns SS51 Oversampling clock fall time — 3.
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Electrical Characteristics 4.12.19.3 SSI Transmitter Timing with External Clock Figure 88 depicts the SSI transmitter external clock timing and Table 75 lists the timing parameters for the transmitter timing with the external clock. SS22 SS25 SS23 SS26 SS24 AUDx_TXC (Input) SS27 SS29 AUDx_TXFS (bl) (Input) SS33 SS31 AUDx_TXFS (wl) (Input) SS39 SS37 SS38 AUDx_TXD (Output) SS45 SS44 AUDx_RXD (Input) Note: AUDx_RXD Input in Synchronous mode only SS46 Figure 88.
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Electrical Characteristics Table 75. SSI Transmitter Timing with External Clock (continued) ID Parameter Min Max Unit Synchronous External Clock Operation SS44 AUDx_RXD setup before AUDx_TXC falling 10.0 — ns SS45 AUDx_RXD hold after AUDx_TXC falling 2.0 — ns SS46 AUDx_RXD rise/fall time — 6.0 ns NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0).
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Electrical Characteristics Table 76. SSI Receiver Timing with External Clock ID Parameter Min Max Unit 81.4 — ns External Clock Operation SS22 AUDx_TXC/AUDx_RXC clock period SS23 AUDx_TXC/AUDx_RXC clock high period 36 — ns SS24 AUDx_TXC/AUDx_RXC clock rise time — 6.0 ns SS25 AUDx_TXC/AUDx_RXC clock low period 36 — ns SS26 AUDx_TXC/AUDx_RXC clock fall time — 6.0 ns SS28 AUDx_RXC high to AUDx_TXFS (bl) high –10 15.
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Electrical Characteristics 4.12.20 UART I/O Configuration and Timing Parameters 4.12.20.1 UART RS-232 I/O Configuration in Different Modes The i.MX 6Dual/6Quad UART interfaces can serve both as DTE or DCE device. This can be configured by the DCEDTE control bit (default 0 – DCE mode). Table 77 shows the UART I/O configuration based on the enabled mode. Table 77. UART I/O Configuration vs.
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Electrical Characteristics 4.12.20.2 UART RS-232 Serial Mode Timing The following sections describe the electrical information of the UART module in the RS-232 mode. 4.12.20.2.1 UART Transmitter Figure 90 depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit format. Table 78 lists the UART RS-232 serial mode transmit timing characteristics.
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Electrical Characteristics 4.12.20.2.3 UART IrDA Mode Timing The following subsections give the UART transmit and receive timings in IrDA mode. UART IrDA Mode Transmitter Figure 92 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 80 lists the transmit timing characteristics. UA3 UA3 UA4 UA3 UA3 UARTx_TX_DATA (output) Start Bit Bit 0 Bit 1 Bit 3 Bit 2 Bit 4 Bit 5 Bit 6 POSSIBLE PARITY BIT Bit 7 STOP BIT Figure 92.
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Electrical Characteristics 4.12.21 USB HSIC Timings This section describes the electrical information of the USB HSIC port. NOTE HSIC is a DDR signal. The following timing specification is for both rising and falling edges. 4.12.21.1 Transmit Timing Tstrobe USB_H_STROBE Todelay Todelay USB_H_DATA Figure 94. USB HSIC Transmit Waveform Table 82. USB HSIC Transmit Parameters Name Parameter Min Max Unit Comment 4.166 4.
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Electrical Characteristics 4.12.22 USB PHY Parameters This section describes the USB-OTG PHY and the USB Host port PHY parameters. The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision 2.0 OTG, USB Host with the amendments below (On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification is not applicable to Host port).
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Boot Mode Configuration 5 Boot Mode Configuration This section provides information on boot mode configuration pins allocation and boot devices interfaces allocation. 5.1 Boot Mode Configuration Pins Table 84 provides boot options, functionality, fuse values, and associated pins. Several input pins are also sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
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Boot Mode Configuration Table 84.
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Boot Mode Configuration Table 85.
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Package Information and Contact Assignments 6 Package Information and Contact Assignments This section includes the contact assignment information and mechanical package drawing. 6.1 Signal Naming Convention The signal names of the i.MX6 series of products are standardized to align the signal names within the family and across the documentation.
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Package Information and Contact Assignments 6.2.1.1 21 x 21 mm Lidded Package Figure 96 and Figure 97 show the top, bottom, and side views of the 21 × 21 mm lidded package. Figure 96. 21 x 21 mm Lidded Package Top, Bottom, and Side Views (Sheet 1 of 2) i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev.
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Package Information and Contact Assignments Figure 97. 21 x 21 mm Lidded Package Top, Bottom, and Side Views (Sheet 2 of 2) i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev.
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Package Information and Contact Assignments 6.2.2 21 x 21 mm Ground, Power, Sense, and Reference Contact Assignments Table 86 shows the device connection list for ground, power, sense, and reference contact signals. Table 86.
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Package Information and Contact Assignments Table 86.
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Package Information and Contact Assignments Table 86. 21 x 21 mm Supplies Contact Assignment (continued) Supply Rail Name Ball(s) Position(s) Remark VDDHIGH_CAP H10, J10 Secondary supply for the 2.5 V domain (internal regulator output—requires capacitor if internal regulator is used) VDDHIGH_IN H9, J9 Primary supply for the 2.
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Package Information and Contact Assignments Table 87.
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Package Information and Contact Assignments Table 87.
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Package Information and Contact Assignments Table 87.
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Package Information and Contact Assignments Table 87.
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Package Information and Contact Assignments Table 87.
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Package Information and Contact Assignments Table 87.
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Package Information and Contact Assignments Table 87.
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Package Information and Contact Assignments Table 87.
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Package Information and Contact Assignments Table 87.
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Package Information and Contact Assignments Table 87.
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Package Information and Contact Assignments Table 87.
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Package Information and Contact Assignments 6.2.4 Signals with Different Reset States For most of the signals, the state during reset is same as the state after reset, given in Out of Reset Condition column of Table 87, “21 x 21 mm Functional Contact Assignments”. However, there are few signals for which the state during reset is different from the state after reset. These signals along with their state during reset are given in Table 88. Table 88.
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Package Information and Contact Assignments Table 88. Signals with Differing Before Reset and After Reset States (continued) Before Reset State Ball Name Input/Output Value EIM_LBA Input PD (100K) EIM_RW Input PD (100K) EIM_WAIT Input PD (100K) GPIO_17 Output Drive state unknown (x) GPIO_19 Output Drive state unknown (x) KEY_COL0 Output Drive state unknown (x) i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev.
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GND VDDUSB_CAP USB_H1_DN PMIC_STBY_REQ BOOT_MODE1 SD3_DAT7 SD3_DAT1 NANDF_CS0 NANDF_D2 SD4_DAT2 SD1_DAT3 SD2_CMD RGMII_TD1 EIM_D17 PCIE_VPTX VDD_SNVS_CAP GND VDD_SNVS_IN SATA_VPH SATA_VP NVCC_SD3 NVCC_NANDF NVCC_SD1 NVCC_SD2 NVCC_RGMII GND EIM_D20 EIM_D19 EIM_A24 GND PCIE_VPH EIM_A19 GND JTAG_TDO EIM_A22 GND JTAG_TDI EIM_A17 CSI_CLK0M DSI_REXT EIM_EB3 CSI_CLK0P GND EIM_D28 CSI_D3M DSI_D0M EIM_D24 CSI_D3P DSI_D0P EIM_D27 EIM_D26 EIM_D22 EIM_EB2 RGMII_TD2 SD2_DAT1
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NXP Semiconductors CSI0_DAT4 CSI0_VSYNC CSI0_DAT7 CSI0_DAT6 CSI0_DAT9 CSI0_DAT8 NVCC_CSI GND VDDARM23_IN GND CSI0_PIXCLK CSI0_DAT5 CSI0_DATA_EN CSI0_MCLK GPIO_19 GPIO_18 NVCC_GPIO GND VDDARM23_IN GND GND VDDARM23_IN GND HDMI_VPH CSI0_DAT18 CSI0_DAT15 CSI0_DAT14 CSI0_DAT11 CSI0_DAT12 CSI0_DAT10 M GND VDDARM23_IN GND HDMI_VP CSI0_DAT19 GND CSI0_DAT16 CSI0_DAT17 GND CSI0_DAT13 L GND VDDARM23_IN GND NVCC_MIPI HDMI_D0P HDMI_D0M HDMI_D2P HDMI_D2M HDMI_DDCCEC HDMI_HPD K
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LVDS1_TX1_N LVDS1_TX3_N LVDS1_TX3_P DRAM_D3 DRAM_D10 GND DRAM_D17 DRAM_D23 GND LVDS1_TX2_P GND DRAM_D6 DRAM_D12 DRAM_D14 DRAM_D16 DRAM_DQM2 DRAM_D18 DRAM_SDQS3_B DRAM_D45 DRAM_D57 DRAM_D41 DRAM_D42 DRAM_SDQS7 GND DRAM_D38 DRAM_D56 DRAM_D33 DRAM_DQM4 DRAM_SDQS7_B DRAM_D32 DRAM_SDODT1 GND GND DRAM_SDWE DRAM_D61 DRAM_A10 DRAM_RAS DRAM_D60 DRAM_A2 DRAM_A1 GND GND DRAM_A8 DRAM_D52 DRAM_A14 DRAM_SDBA2 W LVDS0_TX2_P V DRAM_D25 DRAM_D19 DRAM_D21 DRAM_D20 DRAM_RESET GN
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1 NXP Semiconductors DRAM_D5 DRAM_D0 DRAM_SDQS0_B GND DRAM_D8 DRAM_SDQS1 GND DRAM_SDQS2 DRAM_D29 GND DRAM_D30 DRAM_A12 GND GND DRAM_D1 DRAM_SDQS0 DRAM_D7 DRAM_D9 DRAM_SDQS1_B DRAM_D11 DRAM_SDQS2_B DRAM_D24 DRAM_DQM3 DRAM_D26 DRAM_A9 DRAM_A5 9 8 7 6 5 4 3 2 1 DRAM_A0 DRAM_A6 DRAM_A11 DRAM_D31 14 13 12 11 DRAM_SDQS3 10 DRAM_D28 DRAM_D22 DRAM_D15 DRAM_DQM1 DRAM_D13 DRAM_D2 DRAM_DQM0 DRAM_VREF DRAM_D4 AC GND DRAM_CS1 DRAM_SDQS4 GND DRAM_SDQS5 DRAM_D43 GND DRAM_SDQS6 DRAM_DQM6 DRAM
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Revision History 7 Revision History Table 90 provides a revision history for the i.MX 6Dual/6Quad data sheet. Table 90. i.MX 6Dual/6Quad Data Sheet Document Revision History Rev. Number 6 Date Substantive Change(s) 10/2018 Revision 6 changes: • Table 20, “XTALI and RTC_XTALI DC Parameters,” on page 37, – Row: XTALI input leakage current at startup, IXTALI_STARTUP: Changed from “... driven 32 KHz RTC clock @ 1.1V” to “...driven 24 MHz clock at 1.1V.” • Table 47, “eMMC4.4/4.
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Revision History Table 90. i.MX 6Dual/6Quad Data Sheet Document Revision History (continued) Rev. Number 5 Date Substantive Change(s) 09/2017 Rev. 5 changes include the following: • Changed throughout: – Changed terminology from “floating” to “not connected”. – Removed VADC feature from 19mm x 19mm package. Contact NXP sales and marketing with enablement options. • Section 1, “Introduction” on page 1: Corrected A9 core speed from 1 GHz to 800 MHz. • Section 1.
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Revision History Table 90. i.MX 6Dual/6Quad Data Sheet Document Revision History (continued) Rev. Number 5 (Cont.) Date Substantive Change(s) 09/2017 • Table 20, “XTALI and RTC_XTALI DC Parameters,” on page 37: – Added footnote to RTC_XTALI high level DC input voltage row: “This voltage specification must not be exceeded and …”. Section 4.6.4, “RGMII I/O 2.5V I/O DC Electrical Parameters” on page 38: Added section and table. • Section 4.
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Revision History Table 90. i.MX 6Dual/6Quad Data Sheet Document Revision History (continued) Rev. Number 4 Date Substantive Change(s) 07/2015 • Added footnote to Table 1, “Example Orderable Part Numbers,” on page 3: If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz. • Section 1.2, “Features” changed Five UARTs, from up to 4.0 Mbps, to up to 5.0 Mbps.
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Revision History Table 90. i.MX 6Dual/6Quad Data Sheet Document Revision History (continued) Rev. Number Rev. 3 Rev. 2.3 Date Substantive Change(s) 02/2014 • Updates throughout for Silicon revision D, include: - Figure 1 Part number nomenclature diagram. - Example Orderable Part Number tables, Table 1 • Feature description for Miscellaneous IPs and interfaces; SSI and ESAI. • Table 6, UART 1–5 description change: programmable baud rate up to 5 MHz.
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Revision History Table 90. i.MX 6Dual/6Quad Data Sheet Document Revision History (continued) Rev. Number Rev. 2 Date Substantive Change(s) 04/2013 Substantive changes throughout this document are as follows: • Incorporated standardized signal names. This change is extensive throughout. Added reference to EB792, i.MX Signal Name Mapping. • Figures updated to align to standardized signal names. • Aligned references to FCBGA to read FCPBGA throughout document.
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