Datasheet

Electrical Characteristics
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018
NXP Semiconductors 105
4.12.12.2 D-PHY Signaling Levels
The signal levels are different for differential HS mode and single-ended LP mode. Figure 64 shows both
the HS and LP signal levels on the left and right sides, respectively. The HS signaling levels are below
the LP low-level input threshold such that LP receiver always detects low on HS signals.
Figure 64. D-PHY Signaling Levels
LP Line Receiver DC Specifications
V
IL
Input low voltage — — — 550 mV
V
IH
Input high voltage — 920 — — mV
V
HYST
Input hysteresis — 25 — — mV
Contention Line Receiver DC Specifications
V
ILF
Input low fault threshold — 200 — 450 mV
Table 64. Electrical and Timing Information (continued)
Symbol Parameters Test Conditions Min Typ Max Unit
HS Vout
Range
HS Vcm
Range
Max V
OD
Min V
OD
V
CMTX,MIN
V
OLHS
V
CMTX,MAX
V
OHHS
LP V
IL
LP
V
OL
LP
V
IH
V
OH,MAX
V
OH,MIN
V
IH
V
IL
LP Threshold
Region
V
GNDSH,MA
X
V
GNDSH,MIN
GND
LP V
OL
HS Differential Signaling
LP Single-ended Signaling