Datasheet

Electrical Characteristics
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018
NXP Semiconductors 117
Figure 84. SPDIF_SR_CLK Timing Diagram
Figure 85. SPDIF_ST_CLK Timing Diagram
4.12.19 SSI Timing Parameters
This section describes the timing parameters of the SSI module. The connectivity of the serial
synchronous interfaces are summarized in Table 72.
NOTE
The terms WL and BL used in the timing diagrams and tables refer to Word
Length (WL) and Bit Length (BL).
Table 72. AUDMUX Port Allocation
Port Signal Nomenclature Type and Access
AUDMUX port 1 SSI 1 Internal
AUDMUX port 2 SSI 2 Internal
AUDMUX port 3 AUD3 External – AUD3 I/O
AUDMUX port 4 AUD4 External – EIM or CSPI1 I/O through IOMUXC
AUDMUX port 5 AUD5 External – EIM or SD1 I/O through IOMUXC
AUDMUX port 6 AUD6 External – EIM or DISP2 through IOMUXC
AUDMUX port 7 SSI 3 Internal
SPDIF_SR_CLK
(Output)
V
M
V
M
srckp
srckph
srckpl
SPDIF_ST_CLK
(Input)
V
M
V
M
stclkp
stclkph
stclkpl