Datasheet

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018
118 NXP Semiconductors
Electrical Characteristics
4.12.19.1 SSI Transmitter Timing with Internal Clock
Figure 86 depicts the SSI transmitter internal clock timing and Table 73 lists the timing parameters for
the SSI transmitter internal clock.
.
Figure 86. SSI Transmitter Internal Clock Timing Diagram
Table 73. SSI Transmitter Timing with Internal Clock
ID Parameter Min Max Unit
Internal Clock Operation
SS1 AUDx_TXC/AUDx_RXC clock period 81.4 — ns
SS2 AUDx_TXC/AUDx_RXC clock high period 36.0 — ns
SS4 AUDx_TXC/AUDx_RXC clock low period 36.0 — ns
SS6 AUDx_TXC high to AUDx_TXFS (bl) high — 15.0 ns
SS8 AUDx_TXC high to AUDx_TXFS (bl) low — 15.0 ns
SS10 AUDx_TXC high to AUDx_TXFS (wl) high — 15.0 ns
SS12 AUDx_TXC high to AUDx_TXFS (wl) low — 15.0 ns
SS14 AUDx_TXC/AUDx_RXC Internal AUDx_TXFS rise time — 6.0 ns
SS15 AUDx_TXC/AUDx_RXC Internal AUDx_TXFS fall time — 6.0 ns
SS16 AUDx_TXC high to AUDx_TXD valid from high impedance — 15.0 ns
SS17 AUDx_TXC high to AUDx_TXD high/low — 15.0 ns
SS18 AUDx_TXC high to AUDx_TXD high impedance — 15.0 ns
SS19
SS1
SS2
SS4
SS3
SS5
SS6
SS8
SS10
SS12
SS14
SS18
SS15
SS17
SS16
SS43
SS42
Note: AUDx_RXD input in synchronous mode only
AUDx_TXC
(Output)
AUDx_TXFS (wl)
(Output)
AUDx_TXFS (bl)
(Output)
AUDx_RXD
(Input)
AUDx_TXD
(Output)