Datasheet

Electrical Characteristics
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018
NXP Semiconductors 119
NOTE
• All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
AUDx_TXC/AUDx_RXC and/or the frame sync
AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.
• All timings are on Audiomux Pads when SSI is being used for data
transfer.
• The terms, WL and BL, refer to Word Length(WL) and Bit Length(BL).
• For internal Frame Sync operation using external clock, the frame sync
timing is the same as that of transmit data (for example, during AC97
mode of operation).
Synchronous Internal Clock Operation
SS42 AUDx_RXD setup before AUDx_TXC falling 10.0 — ns
SS43 AUDx_RXD hold after AUDx_TXC falling 0.0 — ns
Table 73. SSI Transmitter Timing with Internal Clock (continued)
ID Parameter Min Max Unit