Datasheet

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018
158 NXP Semiconductors
Revision History
5
(Cont.)
09/2017 • Table 20, “XTALI and RTC_XTALI DC Parameters,” on page 37:
– Added footnote to RTC_XTALI high level DC input voltage row: “This voltage specification must not be
exceeded and …”.
Section 4.6.4, “RGMII I/O 2.5V I/O DC Electrical Parameters” on page 38: Added section and table.
• Section 4.10, “Multi-Mode DDR Controller (MMDC)” on page 60: Replaced section with new content.
Was: 4.9.4 “DDR SDRAM Specific Parameters (DDR3/DDR3L/LPDDR2)” with timing diagrams and
parameter tables for DDR3/DDR3L/LPDDR2.
• Table 47, “eMMC4.4/4.41 Interface Timing Specification,” on page 77,
– Corrected SD3, uSDHC Input Setup Time, minimum value from 2.6ns to 1.7ns.
– Added footnote to Card Input Clock regarding duty cycle range.
• Table 48, “SDR50/SDR104 Interface Timing Specification,” on page 78: Changes to Min/Max values:
– SD2 min from: 0.3 x tCLK; to: 0.46 x tCLK
– SD2 max from: 0.7 x tCLK to: 0.54 x tCLK
– SD3 min from: 0.3 x tCLK; to: 0.46 x tCLK. Also corrected ID from duplicate SD2 to SD3.
– SD3 max from: 0.7 x tCLK; to: 0.54 x tCLK
– SD5 max from: 1 ns; to: 0.74 ns
• Table 58, “Camera Input Signal Cross Reference, Format, and Bits Per Cycle,” on page 91: Changed
RGB565, 16 bits column heading from 2 cycles to 1 cycle.
• Table 59, “Sensor Interface Timing Characteristics,” on page 94, Sensor Interface Timing characteristics:
Added rows to include Vsync values.
• Table 86, “21 x 21 mm Supplies Contact Assignment,” on page 136: Added description to ZQPAD.
• Table 87, “21 x 21 mm Functional Contact Assignments,” on page 138:
– Changed rows DRAM_SDCLK_0 and DRAM_SDCLK_1, Out of Reset Conditions from “Input–Hi-Z” to
“Output–0”.
– Added description to GPANAIO row: “…output for NXP use only…”
(Revision History table continues on next page.)
Table 90. i.MX 6Dual/6Quad Data Sheet Document Revision History (continued)
Rev.
Number
Date Substantive Change(s)