Datasheet

Revision History
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018
NXP Semiconductors 159
4 07/2015 • Added footnote to Table 1, “Example Orderable Part Numbers,” on page 3: If a 24 MHz input clock is
used (required for USB), the maximum SoC speed is limited to 996 MHz.
• Section 1.2, “Features” changed Five UARTs, from up to 4.0 Mbps, to up to 5.0 Mbps.
• Table 6, “Operating Ranges,” on page 21, Row: run mode: LDO bypassed, removed LDO bypassed for
operation up to 852 MHz.
• Table 6, “Operating Ranges,” on page 21: Row: VDD_HIGH internal regulator, changed minimum
parameter value from 2.8 to 2.7V.
• Table 6, “Operating Ranges,” on page 21: Removed footnote: VDDSOC and VDDPU output voltages
must be set according to this rule: VDDARM-VDDSOC/PU<50mV. This was a duplicate footnote,
renumbered footnotes accordingly.
• Table 6, “Operating Ranges,” on page 21: Changed value: Standby/DSM Mode, VDD_SOC_IN, minimum
voltage, from 0.9V to 1.05V.
• Table 8, “Maximum Supply Currents,” on page 25, Differentiated VDD_ARM_IN, VDD_ARM23_IN, and
VDD_SOC_IN by frequency and by Power Virus/CoreMark maximum current.
• Table 20, “XTALI and RTC_XTALI DC Parameters,” on page 37, Added rows: Input capacitance; Startup
current; and DC input current and their values.
• Table 37, “EIM Bus Timing Parameters,” on page 51, Changed WE4–WE17 minimum and maximum
parameter values from, 0.5 t (k+1)/2-1.25, to
0.5 x t x (k+1)-1.25.
• Table 38, “EIM Asynchronous Timing Parameters Relative to Chip Select
,
,” on page 58 Added to end of
formulas in the minimum, typical, and maximum parameter values for WE31–WE42 and WE45–WE46,
× t. For example from 3-CSN, to 3-CSN × t. Also added maximum value to MAXDTI of 10.
• Table 58, “DDR3/DDR3L Write Cycle,” on page 90, Changed minimum parameter value of DDR17 from
240 to 125; and of DDR18 from 240 to 150.
• Figure 29, “LPDDR2 Command and Address Timing Diagram,” on page 91, LP2 signal cycle reduced.
• Table 62, “LPDDR2 Write Cycle,” on page 93, Changed LP21 minimum and maximum parameter value
from -0.25/+0.25 to 0.8/1.2.
• Figure 33, "ECSPI Master Mode Timing Diagram," on page 70, Added footnote: Note: ECSPIx_MOSI is
always driven (not tri-stated) between actual data transmissions. This limits the ECSPI to be connected
between a single master and a single slave.
• Figure 34, "ECSPI Slave Mode Timing Diagram," on page 71, Added footnote: Note: ECSPIx_MISO is
always driven (not tri-stated) between actual data transmissions. This limits the ECSPI to be connected
between a single master and a single slave.
• Figure 57, "Gated Clock Mode Timing Diagram," on page 92, Corrected IPU2_CSIx_HSYNC trace
drawing.
• Section 4.12.22, “USB PHY Parameters” Specified Battery Charging Specification applies to portable
devices only.
(Revision History table continues on next page.)
Table 90. i.MX 6Dual/6Quad Data Sheet Document Revision History (continued)
Rev.
Number
Date Substantive Change(s)