Datasheet
Electrical Characteristics
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018
NXP Semiconductors 37
4.6.1 XTALI and RTC_XTALI (Clock Inputs) DC Parameters
Table 20 shows the DC parameters for the clock inputs.
NOTE
The Vil and Vih specifications only apply when an external clock source is
used. If a crystal is used, Vil and Vih do not apply.
4.6.2 General Purpose I/O (GPIO) DC Parameters
Table 21 shows DC parameters for GPIO pads. The parameters in Table 21 are guaranteed per the
operating ranges in Table 6, unless otherwise noted.
Table 20. XTALI and RTC_XTALI DC Parameters
Parameter Symbol Test Conditions Min Typ Max Unit
XTALI high-level DC input voltage Vih — 0.8 x NVCC_PLL_OUT — NVCC_PLL_ OUT V
XTALI low-level DC input voltage Vil — 0 — 0.2 V
RTC_XTALI high-level DC input
voltage
Vih — 0.8 — 1.1
(See note 1)
1
This voltage specification must not be exceeded and, as such, is an absolute maximum specification.
V
RTC_XTALI low-level DC input
voltage
Vil — 0 — 0.2 V
Input capacitance C
IN
Simulated data — 5 — pF
XTALI input leakage current at
startup
I
XTALI_STARTUP
Power-on startup for
0.15 msec with a driven
24 MHz clock
at 1.1 V.
2
2
This current draw is present even if an external clock source directly drives XTALI.
— — 600 μA
DC input current I
XTALI_DC
———2.5μA
Table 21. GPIO I/O DC Parameters
Parameter Symbol Test Conditions Min Max Unit
High-level output voltage
1
Voh Ioh = -0.1 mA (DSE
2
= 001, 010)
Ioh = -1 mA
(DSE = 011, 100, 101, 110, 111)
OVDD – 0.15 — V
Low-level output voltage
1
Vol Iol = 0.1 mA (DSE
2
= 001, 010)
Iol = 1mA
(DSE = 011, 100, 101, 110, 111)
—0.15V
High-Level DC input voltage
1,
3
Vih — 0.7 × OVDD OVDD V
Low-Level DC input voltage
1,
3
Vil — 0 0.3 × OVDD V
Input Hysteresis Vhys OVDD = 1.8 V
OVDD = 3.3 V
0.25 — V
Schmitt trigger VT+
3, 4
VT+ — 0.5 × OVDD — V
Schmitt trigger VT–
3, 4
VT– — — 0.5 × OVDD V