Datasheet
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018
40 NXP Semiconductors
Electrical Characteristics
4.6.4.2 DDR3/DDR3L Mode I/O DC Parameters
For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported
DDR3/DDR3L/LPDDR2 Configurations.”
The parameters in Table 24 are guaranteed per the operating ranges in Table 6, unless otherwise noted.
Pull-up/pull-down impedance mismatch MMpupd — -15 +15 %
240 Ω unit calibration resolution Rres — — 10 Ω
Keeper circuit resistance Rkeep — 110 175 kΩ
1
Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
2
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot (see Table 28).
Table 24. DDR3/DDR3L I/O DC Electrical Parameters
Parameters Symbol Test Conditions Min Max Unit
High-level output voltage
Voh
Ioh = -0.1 mA
Voh (DSE = 001)
0.8 × OVDD
1
1
OVDD – I/O power supply (1.425 V–1.575 V for DDR3 and 1.283 V–1.45 V for DDR3L).
—V
Ioh = -1 mA
Voh (for all except DSE = 001)
Low-level output voltage
Vol
Iol = 0.1 mA
Vol (DSE = 001)
—0.2× OVDD V
Iol = 1 mA
Vol (for all except DSE = 001)
Input reference voltage Vref
2
2
Vref – DDR3/DDR3L external reference voltage.
—0.49× OVDD 0.51 × OVDD
DC input Logic High Vih(dc) — Vref+0.1 OVDD V
DC input Logic Low Vil(dc) — OVSS Vref-0.1 V
Differential input Logic High Vih(diff) — 0.2 See Note
3
3
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot (see Table 29).
V
Differential input Logic Low Vil(diff) — See Note
3
-0.2 V
Termination Voltage Vtt Vtt tracking OVDD/2 0.49 × OVDD 0.51 × OVDD V
Input current (no pull-up/down) Iin Vin = 0 or OVDD -2.9 2.9 μA
Pull-up/pull-down impedance mismatch
MMpupd
—-1010%
240 Ω unit calibration resolution Rres — — 10 Ω
Keeper circuit resistance Rkeep — 105 175 kΩ
Table 23. LPDDR2 I/O DC Electrical Parameters
1
(continued)
Parameters Symbol Test Conditions Min Max Unit