Datasheet

Electrical Characteristics
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018
NXP Semiconductors 41
4.6.5 LVDS I/O DC Parameters
The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,
“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.
Table 25 shows the Low Voltage Differential Signaling (LVDS) I/O DC parameters.
4.7 I/O AC Parameters
This section includes the AC parameters of the following I/O types:
• General Purpose I/O (GPIO)
• Double Data Rate I/O (DDR) for LPDDR2 and DDR3/DDR3L modes
•LVDS I/O
The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 4 and
Figure 5.
Figure 4. Load Circuit for Output
Figure 5. Output Transition Time Waveform
Table 25. LVDS I/O DC Parameters
Parameter Symbol Test Conditions Min Max Unit
Output Differential Voltage V
OD
Rload=100 Ω between padP and padN 250 450 mV
Output High Voltage V
OH
I
OH
= 0 mA 1.25 1.6
VOutput Low Voltage V
OL
I
OL
= 0 mA 0.9 1.25
Offset Voltage V
OS
— 1.125 1.375
Test Point
From Output
CL
CL includes package, probe and fixture capacitance
Under Test
0V
OVDD
20%
80%
80%
20%
tr
tf
Output (at pad)