Datasheet

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018
48 NXP Semiconductors
Electrical Characteristics
4.8.2 DDR I/O Output Buffer Impedance
For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported
DDR3/DDR3L/LPDDR2 Configurations.”
Table 33 shows DDR I/O output buffer impedance of i.MX 6Dual/6Quad processors.
Note:
1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.
2. Calibration is done against 240 W external reference resistor.
3. Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.
4.8.3 LVDS I/O Output Buffer Impedance
The LVDS interface complies with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A,
“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.
4.9 System Modules Timing
This section contains the timing and electrical parameters for the modules in each i.MX 6Dual/6Quad
processor.
4.9.1 Reset Timing Parameters
Figure 8 shows the reset timing and Table 34 lists the timing parameters.
Figure 8. Reset Timing Diagram
Table 33. DDR I/O Output Buffer Impedance
Parameter Symbol Test Conditions
Typical
Unit
NVCC_DRAM=1.5 V
(DDR3)
DDR_SEL=11
NVCC_DRAM=1.2 V
(LPDDR2)
DDR_SEL=10
Output Driver
Impedance
Rdrv
Drive Strength (DSE) =
000
001
010
011
100
101
110
111
Hi-Z
240
120
80
60
48
40
34
Hi-Z
240
120
80
60
48
40
34
Ω
SRC_POR_B
CC1
(Input)