Datasheet

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018
82 NXP Semiconductors
Electrical Characteristics
4.12.5.2 RMII Mode Timing
In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference
clock. ENET_RX_EN is used as the ENET_RX_EN in RMII. Other signals under RMII mode include
ENET_TX_EN, ENET0_TXD[1:0], ENET_RXD[1:0] and ENET_RX_ER.
Figure 44 shows RMII mode timings. Table 53 describes the timing parameters (M16–M21) shown in the
figure.
Figure 44. RMII Mode Signal Timing Diagram
Table 53. RMII Signal Timing
ID Characteristic Min Max Unit
M16 ENET_CLK pulse width high 35% 65% ENET_CLK period
M17 ENET_CLK pulse width low 35% 65% ENET_CLK period
M18 ENET_CLK to ENET0_TXD[1:0], ENET_TX_EN invalid 4 — ns
M19 ENET_CLK to ENET0_TXD[1:0], ENET_TX_EN valid — 13.5 ns
M20 ENET_RXD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER to
ENET_CLK setup
4— ns
M21 ENET_CLK to ENET_RXD[1:0], ENET_RX_EN, ENET_RX_ER hold 2 — ns
ENET_CLK (input)
ENET_TX_EN
M16
M17
M18
M19
M20
M21
ENET_RXD[1:0]
ENET0_TXD[1:0] (output)
ENET_RX_ER
ENET_RX_EN (input)