Datasheet

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018
98 NXP Semiconductors
Electrical Characteristics
4.12.10.6.2 LCD Interface Functional Description
Figure 60 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure,
signals are shown with negative polarity. The sequence of events for active matrix interface timing is:
• DI_CLK internal DI clock is used for calculation of other controls.
• IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected).
In active mode, IPP_DISP_CLK runs continuously.
• HSYNC causes the panel to start a new line. (Usually IPUx_DIx_PIN02 is used as HSYNC.)
• VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
(Usually IPUx_DIx_PIN03 is used as VSYNC.)
• DRDY acts like an output enable signal to the CRT display. This output enables the data to be
shifted onto the display. When disabled, the data is invalid and the trace is off.
(DRDY can be used either synchronous or asynchronous generic purpose pin as well.)
Figure 60. Interface Timing Diagram for TFT (Active Matrix) Panels
4.12.10.6.3 TFT Panel Sync Pulse Timing Diagrams
Figure 61 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
the data. All the parameters shown in the figure are programmable. All controls are started by
corresponding internal events—local start points. The timing diagrams correspond to inverse polarity of
the IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC, and DRDY signals.
123 mm–1
HSYNC
VSYNC
HSYNC
LINE 1
LINE 2 LINE 3 LINE 4 LINE n-1 LINE n
DRDY
IPP_DISP_CLK
IPP_DATA