Datasheet

Electrical Characteristics
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018
NXP Semiconductors 99
Figure 61. TFT Panels Timing Diagram—Horizontal Sync Pulse
Figure 62 depicts the vertical timing (timing of one frame). All parameters shown in the figure are
programmable.
Figure 62. TFT Panels Timing Diagram—Vertical Sync Pulse
DI clock
VSYNC
HSYNC
DRDY
D0 D1
IP5o
IP13o
IP9o
IP8o IP8
IP9
Dn
IP10
IP7
IP5
IP6
local start point local start point
local start point
IPP_DISP_CLK
IPP_DATA
IP14
VSYNC
HSYNC
DRDY
Start of frame
End of frame
IP12
IP15
IP13
IP11